公开(公告)号：US20130084818A1

公开(公告)日：2013-04-04

申请号：US13249508

申请日：2011-09-30

申请人： Russell Croman ,  Christopher S. Gregg ,  Dan B. Kasha ,  Michael R. May ,  John Khoury ,  Javier Elenes

发明人： Russell Croman ,  Christopher S. Gregg ,  Dan B. Kasha ,  Michael R. May ,  John Khoury ,  Javier Elenes

IPC分类号： H04W24/00 ,  H04W88/00

CPC分类号： H04W52/0238 ,  H04B1/06 ,  H04W52/0245 ,  Y02D70/40

摘要： In one embodiment, a method includes receiving and processing an incoming radio frequency (RF) signal in a receiver. Based on this signal, an environmental noise level can be determined, where this level corresponds to environmental noise present in an environment in which the receiver is located. Then, if the environmental noise level is substantially greater than receiver-generated noise, power consumption of at least one analog front end component of the receiver can be reduced.

摘要翻译： 在一个实施例中，一种方法包括在接收机中接收和处理输入射频（RF）信号。 基于该信号，可以确定环境噪声电平，其中该电平对应于存在于接收器所处的环境中的环境噪声。 然后，如果环境噪声电平显着大于接收器产生的噪声，则可以减少接收机的至少一个模拟前端部件的功耗。

公开(公告)号：US20130007082A1

公开(公告)日：2013-01-03

申请号：US13173365

申请日：2011-06-30

申请人： Javier Elenes

发明人： Javier Elenes

IPC分类号： G06F17/10 ,  H03M3/02

CPC分类号： H04B1/0021 ,  H03M3/344 ,  H03M3/462 ,  H04B1/001

摘要： A digital radio signal is processed by converting an analog signal to a digital signal, decimating the digital signal using a CIC filter and supplying the decimated digital signal directly to an asynchronous sample rate converter (ASRC). The decimated signal is resampled in the ASRC and the ASRC output is supplied directly to a droop compensation filter to compensate the output of the ASRC. By carefully choosing the response of the CIC filter and the resample rate of the ASRC, aliased artifacts in the pass band can be kept below a threshold magnitude without the need for a channelization filter.

摘要翻译： 数字无线电信号通过将模拟信号转换为数字信号来处理，使用CIC滤波器抽取数字信号并将抽取的数字信号直接提供给异步采样率转换器（ASRC）。 抽样信号在ASRC中重新采样，ASRC输出直接提供给下降补偿滤波器，以补偿ASRC的输出。 通过仔细选择CIC滤波器的响应和ASRC的采样速率，通带中的混叠伪像可以保持在阈值以下，而不需要信道化滤波器。

公开(公告)号：US20110158357A1

公开(公告)日：2011-06-30

申请号：US12649761

申请日：2009-12-30

申请人： Younes Djadi ,  Russell Croman ,  Scott Thomas Haban ,  Javier Elenes

发明人： Younes Djadi ,  Russell Croman ,  Scott Thomas Haban ,  Javier Elenes

IPC分类号： H04L27/06

CPC分类号： H04B1/0028 ,  H04J3/0685

摘要： In an embodiment, a tuner circuit includes circuitry to produce a first DSP frame based on a first RF signal and includes an inter-chip receiver circuit coupled to an inter-chip link and configured to receive an inter-chip frame. The inter-chip receiver circuit is configured to detect a start of frame symbol of the inter-chip frame and to extract a DSP offset and data related to a second DSP frame from the inter-chip frame. The tuner circuit further includes a digital signal processor coupled to the circuitry and to the inter-chip receiver circuit. The digital signal processor is to synchronize the first DSP frame with the second DSP frame based on the start of frame symbol and the digital signal processor offset, the digital signal processor configured to perform a selected antenna diversity operation on the first and second DSP frames to produce an output signal.

摘要翻译： 在一个实施例中，调谐器电路包括基于第一RF信号产生第一DSP帧的电路，并且包括耦合到芯片间链路并被配置为接收片间帧的片间接收器电路。 芯片间接收电路被配置为检测芯片间帧的帧符号的开始，并从芯片间帧提取DSP偏移量和与第二DSP帧有关的数据。 调谐器电路还包括耦合到电路和芯片间接收器电路的数字信号处理器。 数字信号处理器将基于帧符号开始和数字信号处理器偏移来同步第一DSP帧与第二DSP帧，数字信号处理器被配置为在第一和第二DSP帧上执行所选择的天线分集操作， 产生输出信号。

公开(公告)号：US20110158298A1

公开(公告)日：2011-06-30

申请号：US12649911

申请日：2009-12-30

申请人： Younes Djadi ,  Russell Croman ,  Scott Thomas Haban ,  Javier Elenes ,  Gerald Champagne ,  Michael Robert May

发明人： Younes Djadi ,  Russell Croman ,  Scott Thomas Haban ,  Javier Elenes ,  Gerald Champagne ,  Michael Robert May

IPC分类号： H04B1/38 ,  H04L27/00

CPC分类号： H04B1/38

摘要： A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame having a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a portion of the digital data stream and a control channel to carry control data. The transceiver circuit is configurable to send the inter-chip communication frame to an additional tuner circuit through an inter-chip communication link.

摘要翻译： 调谐器电路包括数字信号处理器，用于产生与射频信号相关的数字数据流，以及耦合到数字信号处理器的收发器电路，并且可配置为产生具有起始部分和多个通道的芯片间通信帧。 多个信道包括携带数字数据流的一部分的第一数据信道和用于携带控制数据的控制信道。 收发器电路可配置为通过芯片间通信链路将片间通信帧发送到附加的调谐器电路。

公开(公告)号：US20080287072A1

公开(公告)日：2008-11-20

申请号：US11803892

申请日：2007-05-16

申请人： Javier Elenes ,  Dana Taipale

发明人： Javier Elenes ,  Dana Taipale

IPC分类号： H04B1/38 ,  H03D7/16 ,  H04B1/10

CPC分类号： H03J1/0075

摘要： In one embodiment, the present invention includes a method for receiving an incoming radio frequency (RF) signal in a receiver, estimating a signal-to-noise ratio (SNR) of a constant modulus (CM) signal in the incoming RF signal based on a calculated magnitude of the incoming RF signal, and indicating presence of a modulated signal in the incoming RF signal if the estimated SNR is greater than a threshold.

摘要翻译： 在一个实施例中，本发明包括一种用于在接收机中接收输入射频（RF）信号的方法，基于输入RF信号估计恒定模量（CM）信号的信噪比（SNR），基于 输入RF信号的计算幅度，并且如果估计的SNR大于阈值，则指示在输入RF信号中存在调制信号。

公开(公告)号：US07436252B2

公开(公告)日：2008-10-14

申请号：US11529076

申请日：2006-09-28

申请人： Dana Taipale ,  Javier Elenes

发明人： Dana Taipale ,  Javier Elenes

IPC分类号： H03D1/00

CPC分类号： H03D1/2245

摘要： In one aspect, the present invention includes a method for receiving an amplitude modulation (AM) signal in a receiver and performing a coordinate rotation digital computer (CORDIC) operation in obtaining a demodulated AM signal. The demodulated AM signal may be obtained from a magnitude output of the CORDIC operation or as a real output of a multiplication between a complex baseband signal and a demodulating carrier signal generated in a feedback loop.

摘要翻译： 一方面，本发明包括一种在接收机中接收幅度调制（AM）信号并且在获得解调的AM信号中执行坐标旋转数字计算机（CORDIC）操作的方法。 解调的AM信号可以从CORDIC操作的幅度输出中获得，或者作为在反馈回路中产生的复基带信号和解调载波信号之间的乘法的实际输出。

公开(公告)号：US09001945B2

公开(公告)日：2015-04-07

申请号：US13162164

申请日：2011-06-16

申请人： Javier Elenes ,  Lokesh Duraiappah

发明人： Javier Elenes ,  Lokesh Duraiappah

IPC分类号： H04B7/10 ,  H04L1/02 ,  H04B7/08

CPC分类号： H04B7/0845

摘要： In one embodiment, a method for performing antenna diversity combining for digitally broadcast radio signals includes generating a first signal quality metric for a first signal obtained from an incoming digitally broadcast radio signal received in a first signal path, and similarly generating a second signal quality metric for a second signal obtained from the radio signal received in a second signal path. Then the first and second signals from these paths can be coherently combined based on the signal quality metrics to obtain a combined frequency domain symbol. In some embodiments, this combined frequency domain symbol may be remodulated to a time domain symbol. Also in some embodiments N tuners can be daisy chained to generate a final output that is either a frequency domain symbol of combined sub-carriers, soft bits to a forward error correction (FEC) decoder, or a remodulated time domain symbol. As a further possibility, each of the N tuners can use a different local oscillator (LO) frequency.

摘要翻译： 在一个实施例中，一种用于执行用于数字广播无线电信号的天线分集组合的方法包括为从在第一信号路径中接收的输入数字广播无线电信号获得的第一信号生成第一信号质量度量，并且类似地生成第二信号质量度量 用于从在第二信号路径中接收的无线电信号获得的第二信号。 然后，可以基于信号质量度量将来自这些路径的第一和第二信号相干地组合以获得组合的频域符号。 在一些实施例中，该组合频域符号可以被重新调制为时域符号。 同样在一些实施例中，N个调谐器可以被菊花链链接以产生作为组合子载波的频域符号，到前向纠错（FEC）解码器的软比特或重新调制的时域符号的最终输出。 作为另外的可能性，N个调谐器中的每一个可以使用不同的本地振荡器（LO）频率。

公开(公告)号：US08521099B2

公开(公告)日：2013-08-27

申请号：US11824568

申请日：2007-06-29

申请人： Lawrence Der ,  George Tyson Tuttle ,  Alessandro Piovaccari ,  Chunyu Xin ,  Scott Haban ,  Javier Elenes ,  Dan Kasha ,  Peter Vancorenland

发明人： Lawrence Der ,  George Tyson Tuttle ,  Alessandro Piovaccari ,  Chunyu Xin ,  Scott Haban ,  Javier Elenes ,  Dan Kasha ,  Peter Vancorenland

IPC分类号： H04B1/38

CPC分类号： H04B1/40 ,  H03M3/398 ,  H03M3/40 ,  H03M3/448 ,  H03M3/452 ,  H03M3/50

摘要： A transceiver includes a processor, which is adapted to in a transmit mode of the transceiver, form at least part of a transmitter and in a receive mode of the transceiver, form at least part of a receiver. The transceiver may include at least one analog-to-digital converter to provide digital signals to the processor in both the transmit and receive modes of operation; and the transceiver may include at least one digital-to-analog converter to receive digital signals from the processor in the transmit and receive modes of operation. The processor may be fabricated on an integrated circuit with at least one of the analog-to-digital converters and/or with at least one of the digital-to-analog converters.

摘要翻译： 收发器包括适于处于收发器的发射模式的处理器，形成发射器的至少一部分并且在收发器的接收模式中形成接收器的至少一部分。 收发器可以包括至少一个模拟 - 数字转换器，以在发送和接收操作模式中向处理器提供数字信号; 并且收发器可以包括至少一个数模转换器，以在发送和接收操作模式中从处理器接收数字信号。 处理器可以在与至少一个模数转换器和/或至少一个数模转换器的集成电路上制造。

公开(公告)号：US20130003894A1

公开(公告)日：2013-01-03

申请号：US13172260

申请日：2011-06-29

申请人： Javier Elenes ,  Dana Taipale ,  Dave Anderton

发明人： Javier Elenes ,  Dana Taipale ,  Dave Anderton

IPC分类号： H04L27/00

CPC分类号： H04H60/12 ,  H04L5/0007 ,  H04L27/2662

摘要： A method and apparatus for adjusting the delay of a first data stream relative to a second data stream is disclosed. An apparatus receives first and second data streams having identical content. A timing difference between the first and second data streams is estimated. At least the leading one of the data streams is applied to a sample rate converter. The sample rate converter is configured to receive a data stream at an input sampling rate and to output the data stream at an output sampling rate. Based on the estimated timing difference, delay is applied to the leading one of the data streams by changing the sampling rate of the sampling rate converter. The output sampling rate of the sampling rate converter may be adjusted until both data streams are aligned in time.

摘要翻译： 公开了一种用于调整第一数据流相对于第二数据流的延迟的方法和装置。 一种装置接收具有相同内容的第一和第二数据流。 估计第一和第二数据流之间的定时差。 至少将前导数据流应用于采样率转换器。 采样率转换器被配置为以输入采样率接收数据流，并以输出采样率输出数据流。 基于估计的定时差，通过改变采样率转换器的采样率，将延迟应用于数据流中的一个。 可以调整采样率转换器的输出采样率，直到两个数据流在时间上对准。

公开(公告)号：US08331887B2

公开(公告)日：2012-12-11

申请号：US12650166

申请日：2009-12-30

申请人： George Tyson Tuttle ,  Younes Djadi ,  Russell Croman ,  Scott Thomas Haban ,  Javier Elenes ,  Lokesh Duraiappah

发明人： George Tyson Tuttle ,  Younes Djadi ,  Russell Croman ,  Scott Thomas Haban ,  Javier Elenes ,  Lokesh Duraiappah

IPC分类号： H04B7/08 ,  H04K3/00

CPC分类号： H04B7/0682 ,  H04L25/03866

摘要： In an embodiment, a tuner circuit includes an inter-chip receiver circuit configurable to couple to a first inter-chip communication link to receive a first data stream and includes an analog-to-digital converter configured to convert a radio frequency signal into a digital version of the radio frequency signal. The tuner circuit further includes a digital signal processor coupled to the inter-chip receiver circuit and the analog-to-digital converter. The digital signal processor is configurable to generate an output signal related to at least one of the first data stream and the digital version of the radio frequency signal based on a selected operating mode.

摘要翻译： 在一个实施例中，调谐器电路包括可配置为耦合到第一芯片间通信链路以接收第一数据流的芯片间接收器电路，并且包括被配置为将射频信号转换为数字 版本的射频信号。 调谐器电路还包括耦合到芯片间接收器电路和模数转换器的数字信号处理器。 数字信号处理器可配置为基于所选择的操作模式生成与第一数据流和数字版本的数字版本中的至少一个相关的输出信号。