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    Methods and apparatus for improving security while transmitting a data packet
    21.
    发明申请
    Methods and apparatus for improving security while transmitting a data packet 失效
    用于在传输数据分组时提高安全性的方法和装置

    公开(公告)号：US20070223389A1

    公开(公告)日：2007-09-27

    申请号：US11388011

    申请日：2006-03-23

    申请人： Claude Basso ,  Jean Calvignac ,  Ronald Fuhs ,  Nathaniel Sellin ,  Colin Verrilli ,  Scott Willenborg

    发明人： Claude Basso ,  Jean Calvignac ,  Ronald Fuhs ,  Nathaniel Sellin ,  Colin Verrilli ,  Scott Willenborg

    IPC分类号： H04J1/16 ,  H04L12/66

    CPC分类号： H04L49/9042 ,  H04L49/90 ,  H04L69/22

    摘要： In a first aspect, a first method of transmitting a data packet is provided. The first method includes the steps of (1) for each connection from which a data packet may be transmitted, storing header data corresponding to the connection; (2) employing a user application to form header and payload data of a packet, wherein the user application is associated with a connection from which the packet is to be transmitted; and (3) while transmitting the packet, comparing one or more portions of the packet header data with the header data corresponding to the connection with which the user application is associated. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了发送数据分组的第一种方法。 第一种方法包括以下步骤：（1）对于可以从其发送数据分组的每个连接，存储对应于该连接的头部数据; （2）使用用户应用来形成分组的报头和有效载荷数据，其中所述用户应用与要发送所述分组的连接相关联; 和（3）在发送分组时，将分组报头数据的一个或多个部分与对应于用户应用所关联的连接的报头数据进行比较。 提供了许多其他方面。

    Method and system for flexible network processor scheduler and data flow
    23.
    发明申请
    Method and system for flexible network processor scheduler and data flow 失效
    灵活的网络处理器调度器和数据流的方法和系统

    公开(公告)号：US20070011223A1

    公开(公告)日：2007-01-11

    申请号：US11133477

    申请日：2005-05-18

    申请人： Jean Calvignac ,  Chih-jen Chang ,  Joseph Logan ,  Fabrice Verplanken ,  Daniel Wind

    发明人： Jean Calvignac ,  Chih-jen Chang ,  Joseph Logan ,  Fabrice Verplanken ,  Daniel Wind

    IPC分类号： G06F15/16

    CPC分类号： H04L47/527 ,  H04L47/50 ,  H04L47/522 ,  H04L47/568 ,  H04L47/58

    摘要： A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.

    摘要翻译： 提供了一种用于灵活数据流的网络处理器数据流芯片和方法。 数据流芯片包括多个片上数据传输和调度电路结构。 响应于指标选择数据传输和调度电路结构。 数据传输电路结构可以包括可选择的帧处理和数据传输功能。 可选择的帧处理可以包括剪切和粘贴，完全调度和存储和调度帧处理。 调度功能包括完整的内部调度，与外部调度器进行通信的日历调度以及外部日历调度。 在本发明的另一方面，数据传输功能可以包括用于选择性地提供对数据流芯片资源的特权访问的低延迟和正常等待时间的外部处理器接口。

    LINKING FRAME DATA BY INSERTING QUALIFIERS IN CONTROL BLOCKS
    24.
    发明申请
    LINKING FRAME DATA BY INSERTING QUALIFIERS IN CONTROL BLOCKS 审中-公开
    通过在控制块中插入合格者来连接框架数据

    公开(公告)号：US20070002172A1

    公开(公告)日：2007-01-04

    申请号：US11469390

    申请日：2006-08-31

    申请人： Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    发明人： Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    IPC分类号： H04N11/00

    CPC分类号： H04L49/3081 ,  G06F13/4243 ,  H04L2012/5681

    摘要： A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.

    摘要翻译： 一种通过在控制块中插入限定符来减少存储器访问的方法和系统。 在一个实施例中，系统包括被配置为处理数据帧的处理器。 处理器可以包括多个缓冲器，其被配置为存储数据帧，其中每个数据帧可以与帧控制块相关联。 与数据帧相关联的每个帧控制块可以与一个或多个缓冲器控制块相关联。 每个控制块，例如帧控制块，缓冲器控制块，可以包括包含与当前控制块无关的信息的一个或多个限定符字段。 相反，限定符可以包括与另一个控制块有关的信息。 队列中的最后帧控制块以及与帧控制块相关联的最后一个缓冲器控制块可以包括没有信息的字段，从而减少对这些字段中的访问信息的存储器访问。

    Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms
    28.
    发明申请
    Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms 失效

    公开(公告)号：US20060212563A1

    公开(公告)日：2006-09-21

    申请号：US11418606

    申请日：2006-05-05

    申请人： William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

    发明人： William Boyd ,  Jean Calvignac ,  Chih-Jen Chang ,  Douglas Joseph ,  Renato Recio

    IPC分类号： G06F15/173

    CPC分类号： H04L47/10 ,  H04L47/193 ,  H04L69/12 ,  H04L69/16 ,  H04L69/161 ,  H04L69/162

    摘要： A mechanism for offloading the management of send queues in a split socket stack environment, including efficient split socket queue flow control and TCP/IP retransmission support. As consumers initiate send operations, send work queue entries (SWQEs) are created by an Upper Layer Protocol (ULP) and written to the send work queue (SWQ). The Internet Protocol Suite Offload Engine (IPSOE) is notified of a new entry to the SWQ and it subsequently reads this entry that contains pointers to the data that is to be transmitted. After the data is transmitted and acknowledgments are received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). After the CQE is written, the ULP subsequently processes the entry and removes it from the CQE, freeing up a space in both the SWQ and CQ. The number of entries available in the SWQ are monitored by the ULP so that it does not overwrite any valid entries. Likewise, the IPSOE monitors the number of entries available in the CQ, so as not overwrite the CQ. The flow control between the ULP and the IPSOE is credit based. The passing of CQ credits is the only explicit mechanism required to manage flow control of both the SWQ and the CQ between the ULP and the IPSOE.

    Apparatus and method for efficiently modifying network data frames
    30.
    发明申请
    Apparatus and method for efficiently modifying network data frames 失效

    公开(公告)号：US20060146881A1

    公开(公告)日：2006-07-06

    申请号：US11030344

    申请日：2005-01-06

    申请人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Chih-jen Chang ,  Fabrice Verplanken

    IPC分类号： H04J3/00

    CPC分类号： H04L49/901 ,  H04L49/90 ,  H04L49/9021

    摘要： Apparatus and method for storing network frame data which is to be modified. A plurality of buffers stores the network data which is arranged in a data structure identified by a frame control block and buffer control block. A plurality of buffer control blocks associated with each buffer storing the frame data establishes a sequence of the buffers. Each buffer control block has data for identifying a subsequent buffer within the sequence. The first buffer is identified by a field of a frame control block as well as the beginning and ending address of the frame data. The frame data can be modified without rewriting the data to memory by altering the buffer control block and/or frame control block contents without having to copy or rewrite the data in order to modify it.