利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

57 条记录 (耗时 0.024 秒)

    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position
    1.
    发明申请
    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效
    网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置

    公开(公告)号：US20060101172A1

    公开(公告)日：2006-05-11

    申请号：US11320277

    申请日：2005-12-27

    申请人： Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    发明人： Claude Basso ,  Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    IPC分类号： G06F5/00

    CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

    摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

    摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

    LINKING FRAME DATA BY INSERTING QUALIFIERS IN CONTROL BLOCKS
    2.
    发明申请
    LINKING FRAME DATA BY INSERTING QUALIFIERS IN CONTROL BLOCKS 审中-公开
    通过在控制块中插入合格者来连接框架数据

    公开(公告)号：US20070002172A1

    公开(公告)日：2007-01-04

    申请号：US11469390

    申请日：2006-08-31

    申请人： Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    发明人： Jean Calvignac ,  Marco Heddes ,  Joseph Logan ,  Fabrice Verplanken

    IPC分类号： H04N11/00

    CPC分类号： H04L49/3081 ,  G06F13/4243 ,  H04L2012/5681

    摘要： A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.

    摘要翻译： 一种通过在控制块中插入限定符来减少存储器访问的方法和系统。 在一个实施例中，系统包括被配置为处理数据帧的处理器。 处理器可以包括多个缓冲器，其被配置为存储数据帧，其中每个数据帧可以与帧控制块相关联。 与数据帧相关联的每个帧控制块可以与一个或多个缓冲器控制块相关联。 每个控制块，例如帧控制块，缓冲器控制块，可以包括包含与当前控制块无关的信息的一个或多个限定符字段。 相反，限定符可以包括与另一个控制块有关的信息。 队列中的最后帧控制块以及与帧控制块相关联的最后一个缓冲器控制块可以包括没有信息的字段，从而减少对这些字段中的访问信息的存储器访问。

    Longest prefix match (LPM) algorithm implementation for a network processor
    5.
    发明申请
    Longest prefix match (LPM) algorithm implementation for a network processor 失效
    用于网络处理器的最长前缀匹配（LPM）算法实现

    公开(公告)号：US20050144553A1

    公开(公告)日：2005-06-30

    申请号：US11045634

    申请日：2005-01-28

    申请人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

    发明人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

    IPC分类号： G06F17/30 ,  G06F17/00

    CPC分类号： G06F17/30985 ,  H04L45/7457 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99936 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99945

    摘要： Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first: match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.

    摘要翻译： 当搜索具有可变长度模式或前缀的表时，用于查找最长前缀的新型数据结构，方法和装置匹配搜索。 要找到完全匹配或最佳匹配前缀，模式必须一次比较一下，直到找到完全匹配或第一个匹配。 这需要“n”个比较或存储器访问来识别最接近的匹配模式。 树的建立方式使得匹配结果保证是最佳匹配，无论是完全匹配还是最长匹配前缀。 使用所有鸟的踪迹和相关的前缀长度可以确定路线中正确的前缀结果。 通过构建，搜索树在步道或树的步行期间在第一次比较之前或之后提供最佳的匹配前缀。

    Full match (FM) search algorithm implementation for a network processor
    6.
    发明申请
    Full match (FM) search algorithm implementation for a network processor 失效
    网络处理器的完全匹配（FM）搜索算法实现

    公开(公告)号：US20050076010A1

    公开(公告)日：2005-04-07

    申请号：US10650327

    申请日：2003-08-28

    申请人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

    发明人： Brian Bass ,  Jean Calvignac ,  Marco Heddes ,  Antonios Maragkos ,  Piyush Patel ,  Michael Siegel ,  Fabrice Verplanken

    IPC分类号： G06F17/30 ,  H04L12/46 ,  H04L12/56 ,  G06F7/00

    CPC分类号： H04L45/742 ,  H04L45/7453 ,  Y10S707/99933 ,  Y10S707/99934 ,  Y10S707/99935 ,  Y10S707/99936 ,  Y10S707/99937 ,  Y10S707/99943 ,  Y10S707/99945

    摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBS) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.

    摘要翻译： 用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。 输入密钥，对密钥执行散列函数，访问直接表（DT），并通过模式搜索控制块（PSCBS）走树，直到到达叶。 搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。 检索所需的两个密钥和相应的信息都存储在Patricia树结构中。 散列函数提供密钥的比特到散列密钥的比特的n> n映射。 用于存储散列键和树中相关信息的数据结构称为叶。 每个叶对应于与输入键完全匹配的单个键。 叶包含关键以及其他信息。 叶片的长度是可编程的，密钥的长度也是可编程的。 叶存储在随机存取存储器中，并被实现为单个存储器条目。 如果键位于直接表中，则称为直接叶。

    Controller for multiple instruction thread processors
    10.
    发明申请
    Controller for multiple instruction thread processors 失效
    多指令线程处理器的控制器

    公开(公告)号：US20050022196A1

    公开(公告)日：2005-01-27

    申请号：US10915983

    申请日：2004-08-11

    申请人： Gordon Davis ,  Marco Heddes ,  Ross Leavens ,  Fabrice Verplanken

    发明人： Gordon Davis ,  Marco Heddes ,  Ross Leavens ,  Fabrice Verplanken

    IPC分类号： G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F9/52 ,  G06F15/16

    CPC分类号： G06F9/3802 ,  G06F9/3851

    摘要： A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.

    摘要翻译： 机制控制多线程处理器，使得当第一线程遇到第一预定义时间间隔的等待时间事件时，临时控制在第一预定义时间间隔的持续时间内被传送到备用执行线程，然后返回到原始线程。 当遇到第二个预定义时间间隔的延迟事件时，机制将授权对备用执行线程的完全控制。 第一预定时间间隔称为短延迟事件，而第二时间间隔称为长延迟事件。