公开(公告)号：US07299372B2

公开(公告)日：2007-11-20

申请号：US10912481

申请日：2004-08-05

申请人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  Michael Fan Wang

发明人： Jeffrey Douglas Brown ,  Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  Michael Fan Wang

IPC分类号： G06F1/28

CPC分类号： G06F1/3203

摘要： The present invention provides for controlling the power consumption of an element. A first power control command is issued by software for the element. It is determined if the power control command corresponds to an allowable power control state for that element as defined by the hardware. If the power control command is not an allowable power control state for that element, the hardware sets the power control at a higher level than the power control state issued by the software. The software is real time software, and the software also sets minimally acceptable activity control states. A hierarchy of power consumption is defined for different elements of a chip by software, which provides the minimum level of power consumption by any element or sub-element on a chip.

摘要翻译： 本发明提供用于控制元件的功耗。 第一个功率控制命令由该元件的软件发出。 确定功率控制命令是否对应于由硬件定义的该元件的容许功率控制状态。 如果功率控制命令不是该元件的允许功率控制状态，则硬件将功率控制设置在比由软件发出的功率控制状态更高的水平。 该软件是实时软件，软件还设置了最低限度可接受的活动控制状态。 通过软件为芯片的不同元件定义功耗层级，其通过芯片上的任何元件或子元件提供最低功耗水平。

公开(公告)号：US07725618B2

公开(公告)日：2010-05-25

申请号：US10902474

申请日：2004-07-29

申请人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

发明人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

摘要翻译： 本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。 接收到存储器屏障命令并接收存储器命令。 内存命令是根据内存屏障命令执行的。 基于内存障碍命令启动总线操作。 基于总线操作接收总线操作确认。 基于总线操作确认执行存储器障碍命令。 在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。

公开(公告)号：US07233998B2

公开(公告)日：2007-06-19

申请号：US09816004

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US07114035B2

公开(公告)日：2006-09-26

申请号：US10655365

申请日：2003-09-04

申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  James Allan Kahle ,  David Shippy ,  Thuong Quang Truong ,  Takeshi Yamazaki

IPC分类号： G06F12/00

CPC分类号： G06F12/126

摘要： The present invention provides for selectively overwriting sets of a cache as a function of a replacement management table and a least recently used function. A class identifier is created as a function of an address miss. A replacement management table is employable to read the class identifier to create a tag replacement control indicia. The cache, comprising a plurality of sets, is employable to disable the replacement of at least one of the plurality of sets as a function of the tag replacement control indicia.

摘要翻译： 本发明提供了根据替换管理表和最近最少使用的功能来选择性地覆盖高速缓存的集合。 根据地址未命中创建类标识符。 替换管理表可用于读取类标识符以创建标签替换控制标记。 包括多个集合的高速缓存可用于根据标签替换控制标记来禁用对多个集合中的至少一个的替换。

公开(公告)号：US06809734B2

公开(公告)日：2004-10-26

申请号：US09815558

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

IPC分类号： G06T120

CPC分类号： G06F9/4893 ,  A63F2300/20 ,  A63F2300/538 ,  Y02D10/24

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US07698473B2

公开(公告)日：2010-04-13

申请号：US11029891

申请日：2005-01-05

申请人： Takeshi Yamazaki ,  Tsutomu Horikawa ,  James Allan Kahle ,  Charles Ray Johns ,  Michael Norman Day ,  Peichun Peter Liu

发明人： Takeshi Yamazaki ,  Tsutomu Horikawa ,  James Allan Kahle ,  Charles Ray Johns ,  Michael Norman Day ,  Peichun Peter Liu

IPC分类号： G06F13/28 ,  G06F15/167

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： Methods and apparatus provide for transferring a plurality of data blocks between a shared memory and a local memory of a processor in response to a single DMA command issued by the processor to a direct memory access controller (DMAC), wherein the processor is capable of operative communication with the shared memory and the DMAC is operatively coupled to the local memory.

摘要翻译： 方法和装置提供了响应于处理器向直接存储器访问控制器（DMAC）发出的单个DMA命令，在处理器的共享存储器和本地存储器之间传送多个数据块，其中处理器能够操作 与共享存储器和DMAC的通信可操作地耦合到本地存储器。

公开(公告)号：US07546393B2

公开(公告)日：2009-06-09

申请号：US11695436

申请日：2007-04-02

申请人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

发明人： Michael Norman Day ,  Harm Peter Hofstee ,  Charles Ray Johns ,  Peichum Peter Liu ,  Thuong Quang Truong ,  Takeshi Yamazaki

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： The present invention provides for a system comprising a DMA queue configured to receive a DMA command comprising a tag, wherein the tag belongs to one of a plurality of tag groups. A counter couples to the DMA queue and is configured to increment a tag group count of the tag group to which the tag belongs upon receipt of the DMA command by the DMA queue and to decrement the tag group count upon execution of the DMA command. A tag group count status register couples to the counter and is configured to store the tag group count for each of the plurality of tag groups. And the tag group count status register is further configured to receive a request for a tag group status and to respond to the request for the tag group status.

摘要翻译： 本发明提供一种包括配置成接收包括标签的DMA命令的DMA队列的系统，其中标签属于多个标签组之一。 计数器耦合到DMA队列，并配置为在DMA队列接收到DMA命令时增加标签组所属标签组的标签组计数，并在执行DMA命令时递减标签组计数。 标签组计数状态寄存器耦合到计数器，并被配置为存储多个标签组中的每一个的标签组计数。 并且标签组计数状态寄存器被进一步配置为接收对标签组状态的请求并响应对标签组状态的请求。

公开(公告)号：US07243200B2

公开(公告)日：2007-07-10

申请号：US10891772

申请日：2004-07-15

申请人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

发明人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

IPC分类号： G06F12/00

CPC分类号： G06F13/28

摘要： A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

摘要翻译： 提供了一种用于控制存储器访问的方法，装置和计算机程序。 直接存储器访问（DMA）单元已经在许多总线架构中变得普遍。 然而，管理有限的系统资源已成为多个DMA单元的挑战。 为了管理生成的多个命令并保留依赖关系，使用命令中的嵌入式标志或障碍命令。 这些操作然后可以控制执行命令的顺序，以便保留依赖性。

公开(公告)号：US07720982B2

公开(公告)日：2010-05-18

申请号：US11716845

申请日：2007-03-12

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Peter Hofstee ,  Martin E. Hopkins ,  Charles Ray Johns ,  James Allan Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US07225277B2

公开(公告)日：2007-05-29

申请号：US10655370

申请日：2003-09-04

申请人： Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Quang Truong ,  Asano Shigehiro ,  Takeshi Yamazaki

发明人： Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Quang Truong ,  Asano Shigehiro ,  Takeshi Yamazaki

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： A system and method are provided for setting up a direct memory access for a first processor. The system includes the first processor and a local memory. The local memory is coupled to the first processor. A first direct memory access controller (DMAC) is coupled to the first processor and the local memory. A system memory is in communication with the first DMAC. A second processor is in communication with the first DMAC such that the second processor sets up the first DMAC to handle data transfer between the local memory and the system memory. The second processor is interrupted when the first DMAC finishes handling the data transfer.

摘要翻译： 提供了一种用于为第一处理器建立直接存储器访问的系统和方法。 该系统包括第一处理器和本地存储器。 本地存储器耦合到第一处理器。 第一直接存储器存取控制器（DMAC）耦合到第一处理器和本地存储器。 系统存储器与第一DMAC通信。 第二处理器与第一DMAC通信，使得第二处理器设置第一DMAC来处理本地存储器和系统存储器之间的数据传输。 当第一个DMAC完成处理数据传输时，第二个处理器中断。