公开(公告)号：US5907462A

公开(公告)日：1999-05-25

申请号：US302145

申请日：1994-09-07

申请人： Amitava Chatterjee ,  Charvaka Duvvury ,  Ping Yang ,  Ekanayake Ajith Amerasekera

发明人： Amitava Chatterjee ,  Charvaka Duvvury ,  Ping Yang ,  Ekanayake Ajith Amerasekera

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： A protection device comprising a gate-coupled silicon-controlled rectifier (SCR) (100), SCR (100) comprises an anode (105) formed in n-well (104) and connected to a pad (128) and a cathode (111) connected to ground. A gate-coupled NMOS transistor (120) has a gate (116) connected through a resistive element (118) to ground. A n+ region (112) forms both the cathode (111) and a source of the NMOS transistor (120). N-well (104) forms the drain. Stress voltage is coupled from pad (128) to gate electrode (116) causing NMOS transistor (120) to conduct. This, in turn, triggers SCR (100) which dissipates the stress current at the pad (128). The coupled voltage at gate electrode (116) dissipates within a designed time constant through resistive element (118).

摘要翻译： 一种保护装置，包括栅极耦合的可硅可控整流器（SCR）（100），SCR（100）包括形成在n阱（104）中并连接到焊盘（128）和阴极（111）的阳极 ）连接到地面。 栅极耦合NMOS晶体管（120）具有通过电阻元件（118）连接到地的栅极（116）。 n +区域（112）形成阴极（111）和NMOS晶体管（120）的源极。 N阱（104）形成排水管。 应力电压从焊盘（128）耦合到栅电极（116），导致NMOS晶体管（120）导通。 这反过来又触发SCR（100），其消耗衬垫（128）处的应力电流。 栅极（116）处的耦合电压通过电阻元件（118）在设计的时间常数内消散。

公开(公告)号：US5539233A

公开(公告)日：1996-07-23

申请号：US489704

申请日：1995-06-13

申请人： Ajith Amerasekera ,  Amitava Chatterjee

发明人： Ajith Amerasekera ,  Amitava Chatterjee

IPC分类号： H01L27/02 ,  H01L23/62 ,  H01L27/082

CPC分类号： H01L27/0259

摘要： An npn transistor having a low collector-base breakdown voltage. An emitter region (104, 106) of a first conductivity type is located in a semiconductor substrate (102). A base region (14) of a second conductivity type is located within the emitter region (104,106) and a shallow collector region (18) of the first conductivity type is located within the base region (14). The shallow collector region (18) may be doped with arsenic and/or phosphorus such that the dopant concentration and depth of the shallow collector region (18) provide a low collector-base breakdown voltage.

摘要翻译： 具有低集电极 - 基极击穿电压的npn晶体管。 第一导电类型的发射极区域（104,106）位于半导体衬底（102）中。 第二导电类型的基极区域（14）位于发射极区域（104,106）内，并且第一导电类型的浅集电极区域（18）位于基极区域（14）内。 浅集电极区域（18）可以掺杂有砷和/或磷，使得浅集电极区域（18）的掺杂剂浓度和深度提供低的集电极 - 基极击穿电压。

公开(公告)号：US5517051A

公开(公告)日：1996-05-14

申请号：US376183

申请日：1995-01-20

申请人： Amitava Chatterjee

发明人： Amitava Chatterjee

IPC分类号： H01L27/02 ,  H01L23/62

CPC分类号： H01L27/0251 ,  H01L29/87

摘要： A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58). A gate insulator region (233) is formed over adjacent regions of the semiconductor layer (222) and of the lightly doped region (224) to be interposed between the first (226) and third (230) heavily doped regions, such that the gate insulator region (233) is formed over a junction (236) between the semiconductor layer (222) and the lightly doped region (224). A polysilicon gate layer (237) is formed over the gate insulator region (233) and is electrically coupled to the first node (62).

摘要翻译： 提供用于静电放电保护的第一可控硅整流器结构（220），包括具有第一导电类型和面的轻掺杂半导体层（222）。 在半导体层（222）中形成具有与第一导电类型相反的第二导电类型的轻掺杂区（224）。 具有第二导电类型的第一重掺杂区域（226）在所述半导体层（222）内在所述面处横向地形成并且电耦合到第一节点（62）。 具有第二导电类型的第二重掺杂区域（230）在轻掺杂区域（224）内横向形成，并且电耦合到第二节点（58）。 具有第一导电类型的第三重掺杂区域（228）横向地形成在轻掺杂区域（224）内，以被插入在第一和第二重掺杂区域（226和230）之间并且电耦合到第二节点（58） ）。 栅极绝缘体区域（233）形成在半导体层（222）和轻掺杂区域（224）的相邻区域上，以被插入在第一（226）和第三（230）重掺杂区域之间，使得栅极 绝缘体区域（233）形成在半导体层（222）和轻掺杂区域（224）之间的结（236）上。 多晶硅栅极层（237）形成在栅极绝缘体区域（233）上并且电耦合到第一节点（62）。

公开(公告)号：US08860147B2

公开(公告)日：2014-10-14

申请号：US11944861

申请日：2007-11-26

申请人： Amitava Chatterjee ,  Howard Tigelaar ,  Victor Sutcliffe

发明人： Amitava Chatterjee ,  Howard Tigelaar ,  Victor Sutcliffe

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L27/118

CPC分类号： H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

摘要翻译： 一个实施例涉及包括至少一个半导体器件的集成电路。 集成电路包括与半导体器件的第一端子相关联的第一接触。 第一触点跨越介电层并且将第一端子耦合到在集成电路上水平传送信号的互连线，其中互连线具有第一组成。 集成电路还包括与半导体器件的第二端子相关联的第二触点。 第二接触跨越电介质层并将第二端子耦合到通孔连接到的着陆焊盘，其中着陆焊盘具有不同于第一组成的第二组成。 还公开了其它电路和方法。

公开(公告)号：US20140070361A1

公开(公告)日：2014-03-13

申请号：US13609818

申请日：2012-09-11

申请人： Kamel Benaissa ,  Amitava Chatterjee

发明人： Kamel Benaissa ,  Amitava Chatterjee

IPC分类号： H01L29/06 ,  H01L21/761

CPC分类号： H01L21/761 ,  H01L21/266 ,  H01L21/823493 ,  H01L27/0629 ,  H01L27/0802 ,  H01L29/66166 ,  H01L29/8605

摘要： Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.

公开(公告)号：US20140001526A1

公开(公告)日：2014-01-02

申请号：US13534865

申请日：2012-06-27

申请人： Kaiping Liu ,  Amitava Chatterjee ,  Imran Mahmood Khan

发明人： Kaiping Liu ,  Amitava Chatterjee ,  Imran Mahmood Khan

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L29/66181 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11558 ,  H01L28/60

摘要： An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.

摘要翻译： 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，并且包括用作晶体管栅电极的部分，金属对多晶硅存储电容器的板以及多至多晶硅隧道电容器的板。 由氮化硅顶层下面的二氧化硅层构成的硅化物阻挡膜阻止在电极上形成硅化物包层，而诸如多晶硅对金属电容器的集成电路中的其它多晶硅结构是硅化物 - 包裹 在硅化之后，在剩余的多晶硅结构上沉积电容器电介质，随后形成上部金属板。

公开(公告)号：US07859289B2

公开(公告)日：2010-12-28

申请号：US12831122

申请日：2010-07-06

申请人： Tathagata Chatterjee ,  Amitava Chatterjee

发明人： Tathagata Chatterjee ,  Amitava Chatterjee

IPC分类号： G01R31/28

CPC分类号： G01R31/2621

摘要： A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.

摘要翻译： 一种用于测量MOSFET中的接口陷阱的方法，包括测量在预定频率范围内各种频率的脉冲波形的电荷泵浦电流，产生所测量的电荷泵浦电流相对于预定频率范围的绘制点，确定接口总数 通过计算通过绘制点的最佳拟合线的斜率参与电荷泵浦电流的陷阱。

公开(公告)号：US20080096292A1

公开(公告)日：2008-04-24

申请号：US11584056

申请日：2006-10-20

申请人： Tathagata Chatterjee ,  Amitava Chatterjee

发明人： Tathagata Chatterjee ,  Amitava Chatterjee

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： A method for measuring interface traps in a MOSFET, comprising measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.

摘要翻译： 一种用于测量MOSFET中的接口陷阱的方法，包括测量在预定频率范围上的各种频率的脉冲波形的电荷泵浦电流，产生所测量的电荷泵浦电流相对于预定频率范围的绘制点，确定接口总数 通过计算通过绘制点的最佳拟合线的斜率参与电荷泵浦电流的陷阱。

公开(公告)号：US20080003772A1

公开(公告)日：2008-01-03

申请号：US11848187

申请日：2007-08-30

申请人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

发明人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

IPC分类号： H01L21/76

CPC分类号： H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

公开(公告)号：US20070287239A1

公开(公告)日：2007-12-13

申请号：US11451264

申请日：2006-06-12

申请人： Jong Shik Yoon ,  Amitava Chatterjee ,  Kayvan Sadra ,  Shaopin Tang

发明人： Jong Shik Yoon ,  Amitava Chatterjee ,  Kayvan Sadra ,  Shaopin Tang

IPC分类号： H01L21/338 ,  H01L21/425

CPC分类号： H01L27/1104 ,  H01L27/11

摘要： Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.

摘要翻译： 公开了用于形成具有对称注入的有源区并且减少交叉扩散的SRAM单元的方法。 一种方法包括图案化覆盖在半导体衬底上的抗蚀剂层，以形成对称地位于电池的有源区的相对侧上的抗蚀剂结构，使用第一注入使用抗蚀剂结构作为注入掩模注入一种或多种掺杂剂物质， 衬底相对于第一注入约180度，以及使用抗蚀剂结构作为植入掩模将一种或多种掺杂剂物质注入到半导体衬底中，其中第二注入。 还公开了执行对称角度注入的方法，以在电池内提供减小的交叉扩散，包括在电池的有源区域的相对侧上图案化等间隔的抗蚀剂结构，以同样地遮蔽横向相对的第一和第二倾斜植入物。