公开(公告)号：US20090134471A1

公开(公告)日：2009-05-28

申请号：US11944861

申请日：2007-11-26

Applicant: Amitava Chatterjee ,  Howard Tigelaar ,  Victor Sutcliffe

Inventor： Amitava Chatterjee ,  Howard Tigelaar ,  Victor Sutcliffe

IPC: H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

Abstract translation: 一个实施例涉及包括至少一个半导体器件的集成电路。 集成电路包括与半导体器件的第一端子相关联的第一接触。 第一触点跨越介电层并且将第一端子耦合到在集成电路上水平传送信号的互连线，其中互连线具有第一组成。 集成电路还包括与半导体器件的第二端子相关联的第二触点。 第二接触跨越电介质层并将第二端子耦合到通孔连接到的着陆焊盘，其中着陆焊盘具有不同于第一组成的第二组成。 还公开了其它电路和方法。

公开(公告)号：US20060128142A1

公开(公告)日：2006-06-15

申请号：US11296033

申请日：2005-12-07

Applicant: Caroline Whelan ,  Victor Sutcliffe

Inventor： Caroline Whelan ,  Victor Sutcliffe

IPC: H01L21/4763 ,  H01L21/31

CPC classification number: H01L21/76831 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02126 ,  H01L21/28562 ,  H01L21/3128 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76843

Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.

Abstract translation: 提供了将自组装单层选择性沉积到用于互连结构中的扩散阻挡层的衬底表面的方法，包括以下步骤：将第一自组装单层沉积到所述表面，沉积第二自组装单层 到所述表面的未覆盖部分，随后加热所述基底以除去第一自组装单层。 选择性沉积自组装单层膜的方法被用作集成电路的（双）镶嵌结构中的扩散阻挡层。

公开(公告)号：US08860147B2

公开(公告)日：2014-10-14

申请号：US11944861

申请日：2007-11-26

Applicant: Amitava Chatterjee ,  Howard Tigelaar ,  Victor Sutcliffe

Inventor： Amitava Chatterjee ,  Howard Tigelaar ,  Victor Sutcliffe

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L27/118

CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.

Abstract translation: 一个实施例涉及包括至少一个半导体器件的集成电路。 集成电路包括与半导体器件的第一端子相关联的第一接触。 第一触点跨越介电层并且将第一端子耦合到在集成电路上水平传送信号的互连线，其中互连线具有第一组成。 集成电路还包括与半导体器件的第二端子相关联的第二触点。 第二接触跨越电介质层并将第二端子耦合到通孔连接到的着陆焊盘，其中着陆焊盘具有不同于第一组成的第二组成。 还公开了其它电路和方法。

公开(公告)号：US20080105979A1

公开(公告)日：2008-05-08

申请号：US11971777

申请日：2008-01-09

Applicant: Caroline Whelan ,  Victor Sutcliffe

Inventor： Caroline Whelan ,  Victor Sutcliffe

IPC: H01L23/532

CPC classification number: H01L21/76831 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02126 ,  H01L21/28562 ,  H01L21/3128 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76843

Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.

Abstract translation: 提供了将自组装单层选择性沉积到用于互连结构中的扩散阻挡层的衬底表面的方法，包括以下步骤：将第一自组装单层沉积到所述表面，沉积第二自组装单层 到所述表面的未覆盖部分，随后加热所述基底以除去第一自组装单层。 选择性沉积自组装单层膜的方法被用作集成电路的（双）镶嵌结构中的扩散阻挡层。

公开(公告)号：US20050074961A1

公开(公告)日：2005-04-07

申请号：US10957514

申请日：2004-09-30

Applicant: Gerald Beyer ,  Jean Gueneau de Mussy ,  Karen Maex ,  Victor Sutcliffe

Inventor： Gerald Beyer ,  Jean Gueneau de Mussy ,  Karen Maex ,  Victor Sutcliffe

IPC: H01L21/3065 ,  H01L21/311 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469 ,  H01L21/76

CPC classification number: H01L21/76802 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31633 ,  H01L21/764 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.

Abstract translation: 一种用于生产半导体器件中的气隙的方法及其制造的装置。 气隙的形成部分地通过局部地化学和/或机械地改变第一介电层的性质来实现，使得至少部分所述第一电介质层被局部转化并且可被第一蚀刻物质蚀刻。 电介质材料的局部转化可以在含氧等离子体中的材料的各向异性蚀刻期间进行，或者通过进行氧化步骤（例如，加入氧化剂的UV /臭氧处理或超临界二氧化碳）来实现。 在创建导电线之后实现气隙的形成，或者通过第一蚀刻物质形成阻挡层。 空气隙形成在双镶嵌结构中，靠近镶嵌结构的通孔和/或沟槽。

公开(公告)号：US20050012558A1

公开(公告)日：2005-01-20

申请号：US10921386

申请日：2004-08-18

Applicant: Andrew Marshall ,  Victor Sutcliffe

Inventor： Andrew Marshall ,  Victor Sutcliffe

IPC: G01R31/30 ,  H03B1/00

CPC classification number: G01R31/3016

Abstract: The apparatus for detecting the effects of interconnect resistance and capacitance (RC) in a logic circuit includes a first ring oscillator with the interconnect RC parasitics in a logic circuit and a minimum reference ring oscillator without the interconnect RC parasitic in a logic circuit multiplexed to have common stages to obtain delay with and without the parasitics of the interconnect RC. The frequency difference between the first ring oscillator frequency and the minimum reference ring oscillator frequency is determined to detect the effects of the interconnect RC in the logic circuit.

Abstract translation: 用于检测逻辑电路中的互连电阻和电容（RC）的影响的装置包括具有逻辑电路中的互连RC寄生效应的第一环形振荡器和没有互连RC的最小参考环形振荡器在被多路复用的逻辑电路中寄生 获得具有和不具有互连RC的寄生效应的延迟的共同阶段。 确定第一环形振荡器频率和最小参考环形振荡器频率之间的频率差以检测逻辑电路中的互连RC的影响。

公开(公告)号：US07078352B2

公开(公告)日：2006-07-18

申请号：US10957514

申请日：2004-09-30

Applicant: Gerald Beyer ,  Jean Paul Gueneau de Mussy ,  Karen Maex ,  Victor Sutcliffe

Inventor： Gerald Beyer ,  Jean Paul Gueneau de Mussy ,  Karen Maex ,  Victor Sutcliffe

IPC: H01L21/302

CPC classification number: H01L21/76802 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31633 ,  H01L21/764 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.

Abstract translation: 一种用于生产半导体器件中的气隙的方法及其制造的装置。 气隙的形成部分地通过局部地化学和/或机械地改变第一介电层的性质来实现，使得至少部分所述第一电介质层被局部转化并且可被第一蚀刻物质蚀刻。 电介质材料的局部转化可以在含氧等离子体中的材料的各向异性蚀刻期间进行，或者通过进行氧化步骤（例如，加入氧化剂的UV /臭氧处理或超临界二氧化碳）来实现。 在创建导电线之后实现气隙的形成，或者通过第一蚀刻物质形成阻挡层。 空气隙形成在双镶嵌结构中，靠近镶嵌结构的通孔和/或沟槽。

公开(公告)号：US07728436B2

公开(公告)日：2010-06-01

申请号：US11971777

申请日：2008-01-09

Applicant: Caroline Whelan ,  Victor Sutcliffe

Inventor： Caroline Whelan ,  Victor Sutcliffe

IPC: H01L23/48

CPC classification number: H01L21/76831 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/02126 ,  H01L21/28562 ,  H01L21/3128 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76843

Abstract: A method for selective deposition of self-assembled monolayers to the surface of a substrate for use as a diffusion barrier layer in interconnect structures is provided comprising the steps of depositing a first self-assembled monolayer to said surface, depositing a second self-assembled monolayer to the non-covered parts of said surface and subsequently heating said substrate to remove the first self-assembled monolayer. The method of selective deposition of self-assembled monolayers is applied for the use as diffusion barrier layers in a (dual) damascene structure for integrated circuits.

Abstract translation: 提供了将自组装单层选择性沉积到用于互连结构中的扩散阻挡层的衬底表面的方法，包括以下步骤：将第一自组装单层沉积到所述表面，沉积第二自组装单层 到所述表面的未覆盖部分，随后加热所述基底以除去第一自组装单层。 选择性沉积自组装单层膜的方法被用作集成电路的（双）镶嵌结构中的扩散阻挡层。

公开(公告)号：US07319274B2

公开(公告)日：2008-01-15

申请号：US11387188

申请日：2006-03-22

Applicant: Gerald Beyer ,  Jean Paul Gueneau de Mussy ,  Karen Maex ,  Victor Sutcliffe

Inventor： Gerald Beyer ,  Jean Paul Gueneau de Mussy ,  Karen Maex ,  Victor Sutcliffe

IPC: H01L23/48

CPC classification number: H01L21/76802 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31633 ,  H01L21/764 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for the production of airgaps in semiconductor devices and devices produced using such methods are disclosed. An example semiconductor device includes a damascene stack formed using such methods. The damascene stack includes a patterned dielectric layer including an interconnect structure, where the dielectric layer is formed of a dielectric material including Si, C and O. The damascene stack also includes a converted portion of the dielectric layer, where the converted portion is adjacent to the at least one interconnect structure and has a lower carbon content than the dielectric material. The damascene stack also includes an airgap formed adjacent to the interconnect structure, the airgap being formed by removing at least part of the converted portion using an etch compound.

Abstract translation: 公开了使用这种方法生产半导体器件和器件中的气隙的方法。 示例性的半导体器件包括使用这种方法形成的镶嵌叠层。 镶嵌层包括包括互连结构的图案化电介质层，其中电介质层由包括Si，C和O的电介质材料形成。镶嵌层还包括电介质层的转换部分，其中转换部分与 所述至少一个互连结构并且具有比所述电介质材料低的碳含量。 镶嵌叠层还包括邻近互连结构形成的气隙，气隙通过使用蚀刻化合物去除至少部分转化部分而形成。

公开(公告)号：US20060177990A1

公开(公告)日：2006-08-10

申请号：US11387188

申请日：2006-03-22

Applicant: Gerald Beyer ,  Jean Paul Mussy ,  Karen Maex ,  Victor Sutcliffe

Inventor： Gerald Beyer ,  Jean Paul Mussy ,  Karen Maex ,  Victor Sutcliffe

IPC: H01L21/76 ,  H01L21/4763 ,  H01L21/302

CPC classification number: H01L21/76802 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31633 ,  H01L21/764 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76835 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for the production of airgaps in a semiconductor device and device produced therefrom. The formation of airgaps is accomplished, in part, by chemically and/or mechanically changing the properties of a first dielectric layer locally, such that at least part of said first dielectric layer is converted locally and becomes etchable by a first etching substance. The local conversion of the dielectric material may be achieved during anisotropic etching of the material in oxygen containing plasma or ex-situ by performing an oxidizing step (e.g., a UV/ozone treatment or supercritical carbon dioxide with addition of an oxidizer). Formation of airgaps is achieved after creation of conductive lines and, alternatively, a barrier layer by a first etching substance. The airgaps are formed in a dual damascene structure, near the vias and/or the trenches of the damascene structure.