公开(公告)号：US20130244387A1

公开(公告)日：2013-09-19

申请号：US13420412

申请日：2012-03-14

Applicant: Jin Cho

Inventor： Jin Cho

IPC: H01L21/336 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Methods are provided for forming semiconductor devices. One method includes forming a first layer overlying a bulk semiconductor substrate. A second layer is formed overlying the first layer. A plurality of trenches is etched into the first and second layers. Portions of the second layer that are disposed between the plurality of trenches define a plurality of fins. A gate structure is formed overlying the plurality of fins. The first layer is etched to form gap spaces between the bulk semiconductor substrate and the plurality of fins. The plurality of fins is at least partially supported in position adjacent to the gap spaces by the gate structure. The gap spaces are filled with an insulating material.

Abstract translation: 提供了形成半导体器件的方法。 一种方法包括形成覆盖体半导体衬底的第一层。 第二层形成在第一层上。 多个沟槽被蚀刻到第一层和第二层中。 设置在多个沟槽之间的第二层的部分限定多个鳍。 形成在多个翅片上的栅极结构。 蚀刻第一层以在体半导体衬底和多个鳍之间形成间隙。 多个鳍片通过栅极结构至少部分地支撑在与间隙空间相邻的位置。 间隙空间填充绝缘材料。

公开(公告)号：US20130175583A1

公开(公告)日：2013-07-11

申请号：US13345388

申请日：2012-01-06

Applicant: Lei Yuan ,  Jin Cho ,  Jongwook Kye

Inventor： Lei Yuan ,  Jin Cho ,  Jongwook Kye

IPC: H01L29/78 ,  H01L21/768

CPC classification number: H01L29/4232 ,  H01L21/76834 ,  H01L21/76888 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L29/66477 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fabrication methods for semiconductor device structures are provided. One method for fabricating a semiconductor device structure involves forming a first layer of a first dielectric material overlying a doped region formed in a semiconductor substrate, forming a first conductive contact electrically connected to the doped region within the first layer, forming a dielectric cap on the first conductive contact, forming a second layer of a second dielectric material overlying the dielectric cap and a gate structure overlying the semiconductor substrate, and forming a second conductive contact electrically connected to the gate structure within the second layer.

Abstract translation: 提供半导体器件结构的制造方法。 制造半导体器件结构的一种方法包括形成覆盖形成在半导体衬底中的掺杂区域的第一介电材料的第一层，形成电连接到第一层内的掺杂区域的第一导电接触层， 第一导电接触，形成覆盖在电介质盖上的第二电介质材料的第二层和覆盖在半导体衬底上的栅极结构，以及形成电连接到第二层内的栅极结构的第二导电接触。

公开(公告)号：US20130045580A1

公开(公告)日：2013-02-21

申请号：US13210086

申请日：2011-08-15

Applicant: Jin Cho

Inventor： Jin Cho

IPC: H01L21/336 ,  H01L21/762 ,  B82Y40/00

CPC classification number: H01L21/823431 ,  H01L21/76224 ,  H01L29/66545

Abstract: Methods are provided for fabricating FinFETs that avoid thickness uniformity problems across a die or a substrate. One method includes providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines. The substrate is etched to form a plurality of fins, each of the fins extending uniformly across the width of the chips. An oxide is deposited to fill between the fins and is etched to recess the top of the oxide below the top of the fins. An isolation hard mask is deposited and patterned overlying the plurality of fins and is used as an etch mask to etch trenches in the substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins. The trenches are filled with an insulating material to isolate between adjacent active areas.

Abstract translation: 提供了用于制造FinFET的方法，其避免了晶片或衬底上的厚度均匀性问题。 一种方法包括提供划分成多个芯片的半导体衬底，每个芯片由划线限定。 蚀刻基板以形成多个翅片，每个翅片均匀地延伸穿过芯片的宽度。 沉积氧化物以填充在翅片之间并且被蚀刻以使在该翅片顶部下方的氧化物的顶部凹陷。 隔离硬掩模被沉积并且图案覆盖在多个翅片上并被用作蚀刻掩模以蚀刻限定多个有效区域的衬底中的沟槽，多个有效区域中的每一个包括至少一部分至少一个 翅片 沟槽填充绝缘材料以隔离相邻的活性区域。

公开(公告)号：US08053785B2

公开(公告)日：2011-11-08

申请号：US12468612

申请日：2009-05-19

Applicant: Jin Cho

Inventor： Jin Cho

IPC: H01L31/0312

CPC classification number: H01L29/7391 ,  B82Y10/00 ,  H01L29/122 ,  H01L29/66356 ,  H01L29/66431 ,  H01L29/66977 ,  H01L29/7782

Abstract: A tunneling field effect transistor (TFET) device includes a semiconductor substrate having a layer of relatively intermediate bandgap semiconductor material, a layer of relatively low bandgap semiconductor material overlying the layer of relatively intermediate bandgap semiconductor material, and a layer of relatively high bandgap semiconductor material overlying the layer of relatively low bandgap semiconductor material. The TFET device includes a source region, a drain region, and a channel region defined in the semiconductor substrate. The TFET device also has a gate structure overlying at least a portion of the channel region. The source region is highly doped with an impurity dopant having a first conductivity type, and the drain region is highly doped with an impurity dopant having a second conductivity type. The layer of relatively low bandgap semiconductor material promotes tunneling at a first junction between the source region and the channel region, and the layer of relatively high bandgap semiconductor material inhibits tunneling at a second junction between the source region and the channel region.

Abstract translation: 隧道场效应晶体管（TFET）器件包括具有相对中间带隙半导体材料的层的半导体衬底，覆盖在相对中间的带隙半导体材料层上的相对较低的带隙半导体材料的层以及相对较高的带隙半导体材料层 覆盖相对较低带隙半导体材料的层。 TFET器件包括源极区，漏极区和限定在半导体衬底中的沟道区。 TFET器件还具有覆盖沟道区域的至少一部分的栅极结构。 源区高掺杂有具有第一导电类型的杂质掺杂剂，并且漏区被高掺杂有具有第二导电类型的杂质掺杂物。 相对低的带隙半导体材料的层促进在源极区域和沟道区域之间的第一接合处的隧穿，并且相对较高的带隙半导体材料的层在源极区域和沟道区域之间的第二结点处抑制隧穿。

公开(公告)号：US07871873B2

公开(公告)日：2011-01-18

申请号：US12413174

申请日：2009-03-27

Applicant: Witold Maszara ,  Ming-Ren Lin ,  Jin Cho ,  Zoran Krivokapic

Inventor： Witold Maszara ,  Ming-Ren Lin ,  Jin Cho ,  Zoran Krivokapic

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC classification number: H01L29/66795

Abstract: A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.

Abstract translation: 制造用于半导体器件的半导体鳍片的方法可以通过提供体半导体衬底开始。 该方法通过在体半导体衬底上生长第一外延半导体材料层并通过在第一外延半导体材料层上生长第二外延半导体材料层来继续。 该方法然后在第二外延半导体材料层上产生鳍状图案掩模。 翅片图形掩模具有对应于多个翅片的特征。 接下来，使用鳍图案掩模作为蚀刻掩模，并且使用第一外延半导体材料层作为蚀刻停止层，该方法各向异性地蚀刻第二外延半导体材料的层。 该蚀刻步骤导致由第二外延半导体材料层形成的多个鳍片。

公开(公告)号：US20080039610A1

公开(公告)日：2008-02-14

申请号：US11682806

申请日：2007-03-06

Applicant: Jin KIM ,  Jin Cho ,  Keun Lee ,  Jae Kim

Inventor： Jin KIM ,  Jin Cho ,  Keun Lee ,  Jae Kim

IPC: C08G67/02 ,  C07D303/08

CPC classification number: C08G65/22 ,  C07D303/24 ,  C08G65/2609

Abstract: Disclosed are novel compounds that can be used as an energetic binder used for improving the performance and the properties of a high explosive, and a preparation method thereof. More specifically, provided are glycidyl dinitropropyl formal of chemical formula IV having a nitro group (—NO2) as an energy group and having no hydrogen bonding to carbon to which the nitro group is binding, poly(glycidyl dinitropropyl formal) of chemical formula V polymerized using the glycidyl dinitropropyl formal as a monomer, and a preparation method thereof.

Abstract translation: 公开了可用作提高高爆炸性能和性能的能量粘合剂的新型化合物及其制备方法。 更具体地，提供具有硝基（-NO 2 2 N）作为能量基并且与硝基结合的碳没有氢键的化学式IV的缩水甘油基二硝基丙基甲醛，聚（缩水甘油基 使用缩水甘油基二硝基丙基甲缩醛作为单体聚合的化学式V的二硝基丙基甲醛及其制备方法。

公开(公告)号：US20070108125A1

公开(公告)日：2007-05-17

申请号：US11273053

申请日：2005-11-14

Applicant: Jin Cho ,  Kyu Ahn ,  Kyung Song ,  Kyung Poo

Inventor： Jin Cho ,  Kyu Ahn ,  Kyung Song ,  Kyung Poo

IPC: C02F3/30

CPC classification number: C02F3/301 ,  C02F3/1273 ,  Y02W10/15 ,  Y10S210/903 ,  Y10S210/906

Abstract: Disclosed are a membrane coupled activated sludge method and apparatus operating anoxic/anaerobic processes alternately for removal of nitrogen and phosporus, wherein nitrogen and phosphorous together with organics in the sewage, wastewater, filthy water etc. can be simultaneously removed with an economic and efficient manner, an operation thereof is easy and efficient, a capacity thereof is high and the method is economic due to the reduced operating costs with performing measurement and control of a recycle rate, a recycle time of alternate operation of the anoxic and anaerobic process, an amount of sludge, an amount of aeration and an operation of a blower for an intermittent membrane cleaning.

Abstract translation: 本发明公开了一种膜联合活性污泥法和装置，交替运行缺氧/厌氧过程以去除氮和磷，其中可以以经济和有效的方式同时去除氮和磷以及有机物在污水，废水，污浊水等中 其操作容易且有效，其容量高，并且由于通过进行再循环速率的测量和控制，缺氧和厌氧过程的交替操作的循环时间，降低的操作成本，该方法是经济的， 的污泥，一定量的曝气和用于间歇膜清洗的鼓风机的操作。

公开(公告)号：US20070014045A1

公开(公告)日：2007-01-18

申请号：US11454912

申请日：2006-06-19

Applicant: Ki Kim ,  Dong Kwak ,  Seong Booh ,  Eun Bae ,  Jin Cho

Inventor： Ki Kim ,  Dong Kwak ,  Seong Booh ,  Eun Bae ,  Jin Cho

IPC: G11B17/00

CPC classification number: G11B33/025 ,  G11B33/08

Abstract: A disk drive assembly including a disk drive, a bracket for containing the disk drive, and a damper for absorbing an impact transmitted to the disk drive. The damper may have a shape of a ring to encircle a corner of the disk drive and may be formed of an elastic material to buffer an impact transmitted between the disk drive and the bracket. Particularly, since the width and/or diameter of the damper may be formed with a minimized size, the damper is capable of providing sufficient buffering properties. In addition, the space occupied by the damper may further be minimized. Thus, since the space occupied by the disk drive assembly may be reduced, it is possible to favorably apply the assembly to a portable electronic device.

Abstract translation: 一种磁盘驱动器组件，包括磁盘驱动器，用于容纳磁盘驱动器的支架和用于吸收传递到磁盘驱动器的冲击的阻尼器。 阻尼器可以具有环的形状以环绕盘驱动器的角部，并且可以由弹性材料形成以缓冲在盘驱动器和支架之间传递的冲击。 特别地，由于阻尼器的宽度和/或直径可以以最小的尺寸形成，阻尼器能够提供足够的缓冲性能。 此外，阻尼器占据的空间可进一步减小。 因此，由于可以减小由磁盘驱动器组件占据的空间，所以可以有利地将组件应用于便携式电子设备。

公开(公告)号：US20050032499A1

公开(公告)日：2005-02-10

申请号：US10637868

申请日：2003-08-08

Applicant: Jin Cho

Inventor： Jin Cho

IPC: H03G3/30 ,  H04B1/04 ,  H04B1/16

CPC classification number: H03G3/3042 ,  H04B2001/0416

Abstract: A circuit for detecting the amount of radio frequency power provided by an amplifier. The circuit contains an array of coupled transistors in two power amplifiers, and a log-detector circuit, all resident on a single semiconductor die. The main power amplifier contains the larger array of transistors to amplify the radio frequency signal for feeding to an antenna, and a secondary power amplifier contains a smaller array of transistors to provide a scaled output that is proportional to the amplified radio frequency signal and is used to control the main power amplifier. The log-detector circuit converts the signal from the secondary power amplifier to a full-wave rectified log-linear DC signal that is logarithmically proportional to the controlling signal. The DC signal output from the log-detector circuit is fed to the main power amp to control it.

Abstract translation: 一种用于检测由放大器提供的射频功率量的电路。 该电路包含两个功率放大器中的耦合晶体管阵列，以及所有驻留在单个半导体管芯上的对数检波器电路。 主功率放大器包含较大的晶体管阵列，用于放大射频信号以馈送到天线，次级功率放大器包含较小的晶体管阵列，以提供与放大的射频信号成比例的缩放输出，并被使用 控制主功率放大器。 对数检波器电路将来自次级功率放大器的信号转换成与控制信号成对数比例的全波整流对数线性DC信号。 从对数检波器电路输出的直流信号送到主功率放大器进行控制。

公开(公告)号：US08809184B2

公开(公告)日：2014-08-19

申请号：US13465633

申请日：2012-05-07

Applicant: Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

Inventor： Lei Yuan ,  Jin Cho ,  Jongwook Kye ,  Harry J. Levinson

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/441 ,  H01L23/535

CPC classification number: H01L21/823475 ,  H01L21/76895 ,  H01L23/485 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.

Abstract translation: 本文公开的一种方法包括形成导电耦合到多个晶体管器件的源极/漏极区域的多个源极/漏极接触，其中源极/漏极接触中的至少一个是跨越隔离区域的局部互连结构 并且导电地耦合到第一有源区域中的第一源极/漏极区域和第二有源区域中的第二源极/漏极区域，并且形成覆盖第一和第二有源区域并且暴露至少一部分的图案化掩模层 的局部互连结构位于分离第一和第二有源区域的隔离区域之上。 该方法还包括通过图案化掩模层执行蚀刻工艺以移除局部互连结构的一部分，从而限定位于局部互连结构的剩余部分上方的凹槽，以及在凹部中形成绝缘材料。