公开(公告)号：US20070052007A1

公开(公告)日：2007-03-08

申请号：US11516098

申请日：2006-09-05

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568

摘要： A non-volatile memory device (e.g., a split gate type device) and a method of manufacturing the same are disclosed. The memory device includes an active region on a semiconductor substrate, a pair of floating gates above the active region, a charge storage insulation layer between each floating gate and the active region, a pair of wordlines over the active region and partially overlapping the floating gates, respectively, and a gate insulation film between each wordline and the active region. The method may prevent or reduce the incidence of conductive stringers on the active region between the floating gates, to thereby improve reliability of the memory devices and avoid the active region resistance from being increased due to the stringer.

摘要翻译： 公开了一种非易失性存储器件（例如，分离栅型器件）及其制造方法。 存储器件包括半导体衬底上的有源区，有源区上方的一对浮置栅极，每个浮置栅极和有源区之间的电荷存储绝缘层，在有源区上方的一对字线，并与浮置栅极部分重叠 以及每个字线和有源区之间的栅极绝缘膜。 该方法可以防止或减少浮置栅极之间的有源区域上的导电桁条的入射，从而提高存储器件的可靠性，并避免有源区域电阻由于桁条而增加。

公开(公告)号：US20060151486A1

公开(公告)日：2006-07-13

申请号：US11183975

申请日：2005-07-19

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H05B6/50

CPC分类号： H05B6/6464 ,  H05B6/6411

摘要： A method for controlling microwave output depending upon food weight and food position so as to implement optimized cooking performance in a microwave oven and an apparatus for performing the same. According to the control method for cooking food placed on a turntable in a microwave oven, the control method includes detecting a plurality of sensing values generated based on the food weight during the rotation of the turntable, detecting a food position by comparing the detected sensing values, and controlling the microwave output based on the detected food position.

摘要翻译： 一种用于根据食物重量和食物位置控制微波输出的方法，以便在微波炉中实现优化的烹饪性能以及用于执行微波输出的装置。 根据用于烹调放置在微波炉的转台上的食物的控制方法，控制方法包括检测在转台旋转期间基于食物重量产生的多个感测值，通过比较检测到的感测值来检测食物位置 并且基于检测到的食物位置来控制微波输出。

公开(公告)号：US20060023506A1

公开(公告)日：2006-02-02

申请号：US11196641

申请日：2005-08-02

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： H01L29/66833 ,  G11C16/0466 ,  G11C16/10 ,  H01L29/40117 ,  H01L29/792

摘要： The present invention provides a SONOS type nonvolatile or flash memory device and related programming/erasing methods. The device has a deep well region of a first conductive type that isolates a well region of a second conductive type from a substrate to enhance programming and erasing operation characteristics. In the erasing method, first electrons are erased by one of Hot Hole Injection (e.g., gate-to-drain Hot Hole Injection) or tunneling in a first step, and second electrons that are not erased in the first step are erased by the other of tunneling (e.g., gate-to-body tunneling) or HHI in a second step. Preferably, a time gap intervenes between the first and second steps.

摘要翻译： 本发明提供一种SONOS型非易失性存储器件或闪存器件以及相关的编程/擦除方法。 该器件具有第一导电类型的深阱区，其将第二导电类型的阱区与衬底隔离以增强编程和擦除操作特性。 在擦除方法中，第一步中的第一个电子被热孔注入（例如栅极到漏极热孔注入）或隧道中的一个擦除，第一步中未被擦除的第二个电子被其他的 隧道（例如，门对体隧道）或HHI在第二步。 优选地，时间间隙介于第一和第二步骤之间。

公开(公告)号：US20050151204A1

公开(公告)日：2005-07-14

申请号：US11024438

申请日：2004-12-30

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/76 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L29/7887

摘要： A method of fabricating nonvolatile memory devices is disclosed. A nonvolatile memory device comprises: a polysilicon gate on a semiconductor substrate; a gate oxide layer between the polysilicon gate and the substrate; sidewall floating gates on the bottom of the lateral faces of the polysilicon gate; tunnel oxide layers between the sidewall floating gates and the substrate; block oxide layers between the polysilicon gate and the sidewall floating gates; sidewall spacers on the sidewalls of the polysilicon gate and the sidewall floating gates; source and drain extension regions on the substrate under the sidewall spacers; and source and drain regions adjacent to the source and drain extension regions.

摘要翻译： 公开了一种制造非易失性存储器件的方法。 非易失性存储器件包括：半导体衬底上的多晶硅栅极; 多晶硅栅极和衬底之间的栅氧化层; 多晶硅栅极侧面底部的侧壁浮动栅极; 在侧壁浮动栅极和衬底之间的隧道氧化物层; 多晶硅栅极和侧壁浮栅之间的块状氧化物层; 在多晶硅栅极和侧壁浮动栅极的侧壁上的侧壁间隔物; 源极和漏极延伸区域在侧壁间隔物下的衬底上; 以及与源极和漏极延伸区域相邻的源极和漏极区域。

公开(公告)号：US20050151185A1

公开(公告)日：2005-07-14

申请号：US11026972

申请日：2004-12-30

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42336 ,  H01L29/7885 ,  H01L29/7887

摘要： Semiconductor devices and a fabricating method therefore are disclosed. One example method includes forming a buffer oxide layer and a buffer nitride layer on the top surface of a semiconductor substrate; forming a photoresist pattern on the pad nitride layer and forming a trench by etching the buffer nitride layer, the buffer oxide layer and the semiconductor substrate by a predetermined etch using the photoresist pattern as a mask; forming sidewall floating gates on the lateral faces of the trench; depositing polysilicon on the entire surface of the resulting structure; forming a gate electrode by patterning the polysilicon of the resulting structure; removing the buffer nitride layer and forming a poly oxide layer on the exposed part of the polysilicon of the gate electrode; forming source/drain regions by implanting impurities into the predetermined part of the resulting structure; injecting electric charges into the sidewall floating gates; and forming spacers on the lateral faces of the sidewall floating gates and the gate electrode.

摘要翻译： 因此公开了半导体器件和制造方法。 一种示例性方法包括在半导体衬底的顶表面上形成缓冲氧化物层和缓冲氮化物层; 通过使用光致抗蚀剂图案作为掩模通过预定蚀刻蚀刻缓冲氮化物层，缓冲氧化物层和半导体衬底，在衬垫氮化物层上形成光致抗蚀剂图案并形成沟槽; 在沟槽的侧面上形成侧壁浮动栅极; 在所得结构的整个表面上沉积多晶硅; 通过对所得结构的多晶硅进行构图来形成栅电极; 去除所述缓冲氮化物层并在所述栅电极的所述多晶硅的暴露部分上形成多晶氧化物层; 通过将杂质注入到所得结构的预定部分中来形成源极/漏极区域; 将电荷注入侧壁浮动门; 以及在侧壁浮动栅极和栅极电极的侧面上形成间隔物。

公开(公告)号：US20050142761A1

公开(公告)日：2005-06-30

申请号：US11024724

申请日：2004-12-30

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： A method of fabricating a split gate flash memory device by which stringer generation is prevented. The method includes forming a first gate pattern covered with a cap layer on a semiconductor substrate in an active area, and forming an etchant-resistant layer covering one side of the first gate pattern, the etchant-resistant layer extending to a surface of the substrate to cover one confronting side of a neighboring first gate pattern in the active area. The method also includes forming an insulating layer on an exposed surface of the first gate pattern, and forming a second gate pattern covering the first gate pattern and the insulating layer, the second gate pattern not overlapping the etch-resistant layer. The method further includes removing the etch-resistant layer, and forming a pair of doped regions in the substrate aligned with the first and second gate patterns.

摘要翻译： 一种制造分裂栅极闪存器件的方法，通过该方法防止了桁条的产生。 该方法包括在有源区域中形成在半导体衬底上覆盖有覆盖层的第一栅极图案，以及形成覆盖第一栅极图案的一侧的耐蚀刻层，耐蚀刻层延伸到衬底的表面 以覆盖活动区域中相邻的第一栅极图案的相对侧。 该方法还包括在第一栅极图案的暴露表面上形成绝缘层，以及形成覆盖第一栅极图案和绝缘层的第二栅极图案，第二栅极图案不与抗蚀刻层重叠。 该方法还包括去除耐蚀刻层，以及在与第一和第二栅极图案对准的衬底中形成一对掺杂区域。

公开(公告)号：US20050142757A1

公开(公告)日：2005-06-30

申请号：US11024194

申请日：2004-12-29

申请人： Sang Lee ,  Jin Jung ,  Sung Kwon

发明人： Sang Lee ,  Jin Jung ,  Sung Kwon

IPC分类号： H01L27/115 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/105

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A fabricating method of a nonvolatile memory device is disclosed. A disclosed method comprises: implanting ions into an active region of a semiconductor substrate to form a well of a low voltage transistor and adjust its threshold voltage; implanting ions into an active region of the semiconductor substrate to form a well of a high voltage transistor and adjust its threshold voltage, thereby forming a conductive region; depositing an ONO layer on the semiconductor substrate; patterning and etching the ONO layer to form an ONO structure; and forming a gate oxide layer on the semiconductor substrate.

摘要翻译： 公开了一种非易失性存储器件的制造方法。 所公开的方法包括：将离子注入半导体衬底的有源区以形成低压晶体管的阱并调节其阈值电压; 将离子注入到半导体衬底的有源区中以形成高压晶体管的阱并调整其阈值电压，由此形成导电区; 在半导体衬底上沉积ONO层; 图案化和蚀刻ONO层以形成ONO结构; 以及在所述半导体衬底上形成栅氧化层。

公开(公告)号：US20050139905A1

公开(公告)日：2005-06-30

申请号：US11024796

申请日：2004-12-30

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11531

摘要： A semiconductor device and fabricating method. The semiconductor device includes a semiconductor substrate, a device isolation layer on the semiconductor substrate in a logic area of the semiconductor device defining at least one dummy active area, a first dummy pattern on the device isolation layer, and a second dummy pattern enclosing the first dummy pattern on the device isolation layer.

摘要翻译： 半导体器件及其制造方法。 半导体器件包括半导体衬底，在半导体器件的半导体器件的逻辑区域中的器件隔离层，其限定至少一个虚拟有源区，器件隔离层上的第一虚拟图案，以及包围第一 设备隔离层上的虚拟图案。

公开(公告)号：US20050139897A1

公开(公告)日：2005-06-30

申请号：US11023426

申请日：2004-12-29

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L27/115 ,  G11C16/04

CPC分类号： G11C16/0458

摘要： A non-volatile memory device having sidewall floating gates implementing two bits with just one transistor is disclosed. A disclosed method comprises a non-volatile memory device having a unit cell comprising: a transistor including a polysilicon gate, sidewall floating gates, block oxide layers and source and drain regions; a word line vertically placed on a substrate and connected to the polysilicon gate; and a pair of bit lines orthogonally placed to the word line and connected to the source and drain regions.

摘要翻译： 公开了具有仅具有一个晶体管实现两个位的侧壁浮动栅极的非易失性存储器件。 所公开的方法包括具有单元的非易失性存储器件，包括：晶体管，包括多晶硅栅极，侧壁浮置栅极，块状氧化物层以及源极和漏极区域; 垂直放置在基板上并连接到多晶硅栅极的字线; 以及正交放置在字线上并与源极和漏极区连接的一对位线。

公开(公告)号：US20050087777A1

公开(公告)日：2005-04-28

申请号：US10971828

申请日：2004-10-21

申请人： Jin Jung

发明人： Jin Jung

IPC分类号： H01L21/336 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/66484 ,  H01L29/66575 ,  H01L29/7831

摘要： The present invention relates to a MOS transistor which is capable of compensating the shortcomings of the conventional MOS transistor having three gate electrodes. In order to achieve the object the MOS transistor of the present invention is characterized in that the sidewall gates are made of material having an energy band gap higher than that of the material constituting the main gate or the sidewall gates are implanted with holes (or positive charges) or electrons (or negative charges). The MOS transistor of the present invention includes a gate dielectric layer formed on a semiconductor substrate at a predetermined width, a main gate formed onto a middle of the gate dielectric layer at a width narrower than that of the gate dielectric layer, sidewall insulators formed on both sides of the main gate, sidewall gates formed on the sidewall insulators and the gate dielectric layer extended outward the main gate, the sidewall gates being injected by holes or electrons, and source/drain regions formed outward the sidewall gates within the semiconductor substrate.

摘要翻译： 本发明涉及能够补偿具有三个栅电极的常规MOS晶体管的缺点的MOS晶体管。 为了实现该目的，本发明的MOS晶体管的特征在于，侧壁栅极由具有高于构成主栅极的材料的能带隙的材料制成，或侧壁栅极注入孔（或正极 电荷）或电子（或负电荷）。 本发明的MOS晶体管包括形成在预定宽度的半导体衬底上的栅极电介质层，在栅极电介质层的中间形成的栅极电介质层的宽度窄的栅极电介质层， 主栅极的两侧，形成在侧壁绝缘体上的侧壁栅极和栅极电介质层向外延伸到主栅极，侧壁栅极被空穴或电子注入，以及源极/漏极区域形成在半导体衬底内的侧壁栅极的外侧。