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    Random cache read
    21.
    发明授权
    Random cache read 有权
    随机缓存读取

    公开(公告)号：US07369447B2

    公开(公告)日：2008-05-06

    申请号：US11515629

    申请日：2006-09-05

    Applicant: Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

    Inventor： Benjamin Louie ,  Yunqiu Wan ,  Aaron Yip ,  Jin-Man Han

    IPC: G11C7/00

    CPC classification number: G11C7/1042 ,  G11C7/1051 ,  G11C16/26 ,  G11C2207/2245

    Abstract: A non-volatile memory is described that utilizes a cache read mode of operation, where a next page of memory is being read/sensed from the memory array by the sense amplifiers while a previously read page of memory is being read from the memory I/O buffer, wherein the next page is user selected. This random cache read mode allows for a memory with a random page read capability, in which the address of the next page of data to be read is user selectable, which benefits from the low latency of a cache read mode of operation due to concurrent data sensing and data I/O.

    Abstract translation: 描述了利用高速缓存读取操作模式的非易失性存储器，其中由读出放大器从存储器阵列读取/感测存储器的下一页，同时从存储器I / O缓冲器，其中下一页是用户选择的。 这种随机高速缓存读取模式允许具有随机页面读取功能的存储器，其中要读取的下一页数据的地址是用户可选择的，这受益于由于并发数据而导致的高速缓存读取操作模式的低等待时间 感测和数据I / O。

    Programming memory devices
    22.
    发明授权
    Programming memory devices 有权
    编程存储器件

    公开(公告)号：US07269066B2

    公开(公告)日：2007-09-11

    申请号：US11126790

    申请日：2005-05-11

    Applicant: Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

    Inventor： Dzung H. Nguyen ,  Benjamin Louie ,  Hagop A. Nazarian ,  Aaron Yip ,  Jin-Man Han

    IPC: G11C16/04

    CPC classification number: G11C16/10

    Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.

    Abstract translation: 通过将编程电压施加到包括目标存储器单元的字线，确定目标存储器单元是否被编程来编程存储器件的目标存储器单元，并且如果确定所述编程电压被确定为 目标存储单元未编程。 在制造存储器件之后，可以选择初始编程电压和阶跃电压。

    Memory device trims
    25.
    发明申请
    Memory device trims 有权
    存储设备修剪

    公开(公告)号：US20060015691A1

    公开(公告)日：2006-01-19

    申请号：US10894242

    申请日：2004-07-19

    Applicant: Benjamin Louie ,  Aaron Yip ,  Jin-Man Han

    Inventor： Benjamin Louie ,  Aaron Yip ,  Jin-Man Han

    IPC: G06F12/00

    CPC classification number: G11C16/20 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028

    Abstract: Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or more reference control parameter values for respectively correcting one or more of the base control parameter values of the base trim circuitry for application to the portion of the memory array. The memory device may include an index circuit corresponding to the reference trim circuit. The index circuit is adapted to store one or more index parameter values for respectively selecting the one or more base control parameter values of the base trim circuitry for correction by the one or more reference control parameter values of the reference trim circuit.

    Abstract translation: 提供了方法和装置。 存储器件具有存储器阵列，适用于存储存储器阵列共用的基本控制参数值的基本修剪电路以及与存储器阵列的一部分相对应的参考调整电路。 参考调整电路适于存储一个或多个参考控制参数值，用于分别校正基本调整电路的基本控制参数值中的一个或多个，以供应用于存储器阵列的该部分。 存储器件可以包括对应于参考调整电路的指数电路。 索引电路适于存储一个或多个索引参数值，用于分别选择基本修整电路的一个或多个基本控制参数值，以通过参考调整电路的一个或多个参考控制参数值进行校正。

    Memory device with a decreasing dynamic pass voltage for reducing read-disturb effect
    28.
    发明授权
    Memory device with a decreasing dynamic pass voltage for reducing read-disturb effect 有权
    具有降低的动态通过电压的存储器件，用于降低读取干扰效应

    公开(公告)号：US08120952B2

    公开(公告)日：2012-02-21

    申请号：US12721693

    申请日：2010-03-11

    Applicant: Jin-Man Han

    Inventor： Jin-Man Han

    IPC: G11C16/04

    CPC classification number: G11C11/5642 ,  G11C16/0483

    Abstract: The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying sensing voltages to selected access lines for sensing selected memory cells. The method also includes applying a dynamic pass voltage to unselected access lines while the sensing voltages are applied.

    Abstract translation: 本公开包括用于操作存储器单元的方法，设备，模块和系统。 一种方法实施例包括将感测电压施加到用于感测所选存储器单元的所选择的存取线。 该方法还包括在施加感测电压的同时向未选择的接入线施加动态通过电压。

    METHOD OF STORING DATA ON A FLASH MEMORY DEVICE
    29.
    发明申请
    METHOD OF STORING DATA ON A FLASH MEMORY DEVICE 有权
    在闪存存储器件上存储数据的方法

    公开(公告)号：US20110213918A1

    公开(公告)日：2011-09-01

    申请号：US13103669

    申请日：2011-05-09

    Applicant: Jin-Man Han

    Inventor： Jin-Man Han

    IPC: G06F12/02

    CPC classification number: G11C16/10 ,  G11C8/08 ,  G11C16/3495 ,  G11C2216/14

    Abstract: Methods and apparatus are disclosed, such as those involving a flash memory device. One such method includes storing data on memory cells on a memory block including a plurality of word lines and a plurality of memory cells on the word lines. The word lines comprising one or more bottom edge word lines, one or more top edge word lines, and intermediate word lines between the bottom and top edge word lines. The data is stored first on memory cells on the intermediate word lines. Then, a remaining portion, if any, of the data is stored on memory cells on the bottom edge word lines and/or the top edge word lines. This method enhances the life of the flash memory by preventing a premature failure of memory cells on the bottom or top edge word lines, which can be more prone to failure.

    Abstract translation: 公开了诸如涉及闪存装置的方法和装置。 一种这样的方法包括将存储器单元上的数据存储在包括字线上的多个字线和多个存储器单元的存储器块上。 字线包括一个或多个底边字线，一个或多个顶边字线，以及底边和顶边字线之间的中间字线。 数据首先存储在中间字线上的存储单元上。 然后，数据的剩余部分（如果有的话）被存储在底部边缘字线和/或顶部边缘字线上的存储器单元上。 该方法通过防止底部或顶部边缘字线上的存储器单元的过早故障来增加闪存的寿命，这可能更容易发生故障。

    FLASH MEMORY DEVICE WITH REDUNDANT COLUMNS
    30.
    发明申请
    FLASH MEMORY DEVICE WITH REDUNDANT COLUMNS 有权
    具有冗余色谱柱的闪存存储器件

    公开(公告)号：US20110019474A1

    公开(公告)日：2011-01-27

    申请号：US12898070

    申请日：2010-10-05

    Applicant: Jin-Man Han ,  Aaron Yip

    Inventor： Jin-Man Han ,  Aaron Yip

    IPC: G11C16/06

    CPC classification number: G11C29/846 ,  G11C29/82 ,  G11C2216/30

    Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.

    Abstract translation: 公开了装置和方法，例如涉及闪存装置的装置和方法。 一种这样的装置包括包括多个列的存储块。 每个列包括位线和位线上的多个存储单元。 多个列包括多组常规列和多组冗余列。 该装置还包括多个数据锁存器。 每个数据锁存器被配置为存储从相应的一组常规列读取的数据。 该装置还包括多个冗余数据锁存器。 每个冗余数据锁存器被配置为存储从相应的一组冗余列读取的数据。 该装置还包括多路复用器，其被配置为选择性地从多个数据锁存器和多个冗余数据锁存器输出数据。

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