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    Switching a defective signal line with a spare signal line without shutting down the computer system
    22.
    发明授权
    Switching a defective signal line with a spare signal line without shutting down the computer system 失效
    在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线

    公开(公告)号：US07793143B2

    公开(公告)日：2010-09-07

    申请号：US12098294

    申请日：2008-04-04

    申请人： Edgar R. Cordero ,  James S. Fields, Jr. ,  Kevin C. Gower ,  Eric E. Retter

    发明人： Edgar R. Cordero ,  James S. Fields, Jr. ,  Kevin C. Gower ,  Eric E. Retter

    IPC分类号： G06F11/00

    CPC分类号： G06F11/10 ,  G06F11/2007 ,  G11C29/025 ,  G11C2029/0409

    摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.

    摘要翻译： 一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。 服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。 如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。服务处理器配置与缺陷信号相关联的驱动器/接收器对中的开关控制单元 线路，以便在从存储器控制器开关控制单元接收到命令时能够用备用线路切换有缺陷的信号线。 以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。

    Switching a defective signal line with a spare signal line without shutting down the computer system
    23.
    发明授权
    Switching a defective signal line with a spare signal line without shutting down the computer system 失效
    在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线

    公开(公告)号：US07380161B2

    公开(公告)日：2008-05-27

    申请号：US11056886

    申请日：2005-02-11

    申请人： Edgar R. Cordero ,  James S. Fields, Jr. ,  Kevin C. Gower ,  Eric E. Retter

    发明人： Edgar R. Cordero ,  James S. Fields, Jr. ,  Kevin C. Gower ,  Eric E. Retter

    IPC分类号： G06F11/00

    CPC分类号： G06F11/10 ,  G06F11/2007 ,  G11C29/025 ,  G11C2029/0409

    摘要： A method, computer program product and system for switching a defective signal line with a spare signal line without shutting down the computer system. A service processor monitors error correction code (ECC) check units configured to detect an error in a signal line. If an ECC check unit detects an error rate that exceeds a threshold, then the signal line with such an error rate may be said to be “defective.” The service processor configures switch control units in the driver/receiver pair associated with the defective signal line to be able to switch the defective signal line with a spare line upon receipt of a command from a memory controller switch control unit. In this manner, the system is not deactivated in order to switch a defective signal line with a spare line thereby reducing the time that the processor cannot send information to the memory buffers.

    摘要翻译： 一种用于在不关闭计算机系统的情况下用备用信号线切换有缺陷的信号线的方法，计算机程序产品和系统。 服务处理器监视配置成检测信号线中的错误的纠错码（ECC）检查单元。 如果ECC检查单元检测到错误率超过阈值，则具有这种错误率的信号线可能被认为是“有缺陷的”。 服务处理器配置与缺陷信号线相关联的驱动器/接收器对中的开关控制单元，以便在从存储器控制器开关控制单元接收到命令时能够用备用线切换故障信号线。 以这种方式，为了用备用线切换有缺陷的信号线，系统不被去激活，从而减少处理器不能向存储器缓冲器发送信息的时间。

    Computer system and method of protection for the system's marking store
    25.
    发明授权
    Computer system and method of protection for the system's marking store 失效
    计算机系统和系统标记存储的保护方法

    公开(公告)号：US08650437B2

    公开(公告)日：2014-02-11

    申请号：US12825521

    申请日：2010-06-29

    申请人： Richard E. Fry ,  Marc A. Gollub ,  Luis A. Lastras-Montano ,  Eric E. Retter ,  Kenneth L. Wright

    发明人： Richard E. Fry ,  Marc A. Gollub ,  Luis A. Lastras-Montano ,  Eric E. Retter ,  Kenneth L. Wright

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1048

    摘要： A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.

    摘要翻译： 一种用于控制在具有多个核心处理器和eDRAM缓存和互连总线的中央电子复合体中将标记存储更新的方法和装置，用于将服务处理器用于使用内部标记存储器将存储器控制器固件加载到双通道DDR3存储器控制器。 存储器控制器的加载固件负责使用ECC解码器控制来跟踪ECC错误，由此所述标记存储器由慢ECC解码器写入，并且由快速ECC解码器读取，用于所述存储器控制器的每次读取操作，以提供阻塞机制 用于在更新标记存储时通知标记存储固件，并确保标记存储固件无法写入标记存储，直到标记存储固件看到更新，而不会导致标记存储硬件超时。

    IMPLEMENTING ENHANCED MEMORY RELIABILITY USING MEMORY SCRUB OPERATIONS
    26.
    发明申请
    IMPLEMENTING ENHANCED MEMORY RELIABILITY USING MEMORY SCRUB OPERATIONS 有权
    使用存储器SCRUB操作实现增强的存储器可靠性

    公开(公告)号：US20110029807A1

    公开(公告)日：2011-02-03

    申请号：US12510311

    申请日：2009-07-28

    申请人： Richard E. Fry ,  Marc A. Gollub ,  Eric E. Retter ,  Kenneth L. Wright

    发明人： Richard E. Fry ,  Marc A. Gollub ,  Eric E. Retter ,  Kenneth L. Wright

    IPC分类号： G11C29/08 ,  G06F11/14 ,  G06F11/26

    CPC分类号： G06F11/106

    摘要： A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.

    摘要翻译： 一种用于使用存储器擦除操作来实现增强的存储器可靠性以确定间歇可校正错误的频率的方法和电路，以及提供了所述主题电路所在的设计结构。 间歇性的内存擦除在移动到下一个内存擦除地址之前执行至少两次读取。 跟踪识别出间歇性错误的多个间歇性错误，响应于识别一个失败的读取和一次读取至少两个读取。

    Computer System and Method of Protection for the System's Marking Store
    29.
    发明申请
    Computer System and Method of Protection for the System's Marking Store 失效
    计算机系统和系统标记商店的保护方法

    公开(公告)号：US20110320911A1

    公开(公告)日：2011-12-29

    申请号：US12825521

    申请日：2010-06-29

    申请人： Richard E. Fry ,  Marc A. Gollub ,  Luis A. Lastras-Montano ,  Eric E. Retter ,  Kenneth L. Wright

    发明人： Richard E. Fry ,  Marc A. Gollub ,  Luis A. Lastras-Montano ,  Eric E. Retter ,  Kenneth L. Wright

    IPC分类号： H03M13/09

    CPC分类号： G06F11/1048

    摘要： A method and apparatus for controlling marking store updates in a central electronic complex with a plurality of core processors and eDRAM cache and interconnect bus to a service processor for loading memory controller firmware to dual-channel DDR3 memory controllers with an internal marking store. Loaded firmware of the memory controllers is responsible for tracking of ECC errors using a ECC decoder control whereby said marking store is written by a slow ECC decoder, and read by a fast ECC decoder for every read operation of said memory controllers to provide a blocking mechanism for notifying marking store firmware when the marking store has been updated and which guarantees that marking store firmware cannot write to the marking store until the marking store firmware has seen updates without causing the marking store hardware to time out.

    摘要翻译： 一种用于控制在具有多个核心处理器和eDRAM缓存和互连总线的中央电子复合体中将标记存储更新的方法和装置，用于将服务处理器用于使用内部标记存储器将存储器控制器固件加载到双通道DDR3存储器控制器。 存储器控制器的加载固件负责使用ECC解码器控制来跟踪ECC错误，由此所述标记存储器由慢ECC解码器写入，并且由快速ECC解码器读取，用于所述存储器控制器的每次读取操作，以提供阻塞机制 用于在更新标记存储时通知标记存储固件，并确保标记存储固件无法写入标记存储，直到标记存储固件看到更新，而不会导致标记存储硬件超时。