公开(公告)号：US20090267129A1

公开(公告)日：2009-10-29

申请号：US12498311

申请日：2009-07-06

Applicant: Jong-Pyo KIM ,  Jong-Ho LEE ,  Hyung-Suk JUNG ,  Jung-Hyoung LEE

Inventor： Jong-Pyo KIM ,  Jong-Ho LEE ,  Hyung-Suk JUNG ,  Jung-Hyoung LEE

IPC: H01L29/788 ,  H01L29/51 ,  B32B15/01

CPC classification number: H01L21/28202 ,  H01L21/28185 ,  H01L21/28194 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/94 ,  Y10T428/265

Abstract: A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M'Oy) or amorphous metal oxynitride (M'OyNz).

Abstract translation: 在一个实施例中提供了一种微电子器件的电介质多层结构，其中泄漏电流特性和介电常数得到改善。 电介质多层结构包括由非晶硅酸盐（M1-xSixOy）或无定形硅酸盐氮化物（M1-xSixOyNz）制成的下电介质层，以及形成在下电介质层的顶部上的上电介质层 的无定形金属氧化物（M'Oy）或无定形金属氧氮化物（M'OyNz）。

公开(公告)号：US20080283996A1

公开(公告)日：2008-11-20

申请号：US12121490

申请日：2008-05-15

Applicant: Min-Ho O ,  Jong-Ho LEE ,  Eun-Chul AHN ,  Pyoung-Wan KIM

Inventor： Min-Ho O ,  Jong-Ho LEE ,  Eun-Chul AHN ,  Pyoung-Wan KIM

IPC: H01L23/49 ,  H01L23/538

CPC classification number: H01L24/85 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/78 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package using a chip-embedded interposer substrate is provided. The chip-embedded interposer substrate includes a chip including a plurality of chip pads; a substrate having the chip mounted thereon and including a plurality of redistribution pads for redistributing the chip pads; bonding wires for connecting the chip pads to the redistribution pads; a protective layer having via holes for exposing the redistribution pads while burying the chip and the substrate; and vias connected to the redistribution pads through the via holes. The semiconductor package including chips of various sizes is fabricated using the chip-embedded interposer substrate.

Abstract translation: 提供了使用芯片嵌入式插入器基板的半导体封装。 芯片嵌入式插入器基板包括：包括多个芯片焊盘的芯片; 具有安装在其上的芯片并且包括用于重新分配芯片焊盘的多个再分配焊盘的衬底; 用于将芯片焊盘连接到再分配焊盘的接合线; 保护层，其具有用于在掩埋所述芯片和所述基板的同时露出所述再分布焊盘的通孔; 以及通过通孔连接到再分配焊盘的通孔。 包括各种尺寸的芯片的半导体封装使用芯片嵌入式插入器基板来制造。

公开(公告)号：US20080251825A1

公开(公告)日：2008-10-16

申请号：US12101143

申请日：2008-04-10

Applicant: Jong-Ho LEE

Inventor： Jong-Ho LEE

IPC: H01L29/78 ,  H01L27/108

CPC classification number: H01L29/42392 ,  G11C11/403 ,  H01L27/10876 ,  H01L29/7827 ,  H01L29/7831 ,  H01L29/78642 ,  H01L29/78648

Abstract: A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes a semiconductor pillar, a gate insulating layer formed on a portion of a surface of the semiconductor pillar, a gate electrode formed on the gate insulating layer, and source/drain regions formed on portions of the semiconductor pillar where the gate electrode is not formed, in which the gate electrode includes a first gate electrode, a second gate electrode, and an inter-gate insulating layer, in which the first gate electrode has a work function higher than that of the second gate electrode, in which the inter-gate insulating layer is formed between the first gate electrode and the second gate electrode, and in which the first gate electrode and the second gate electrode are electrically connected by a contact or a metal interconnection line. A portion of the second gate electrode having the work function lower than that of the first gate electrode is overlapped by the drain region. Accordingly, the gate electrode of the pillar-type FET is formed using a material having a high work function, so that the threshold voltage can be increased and the work function of the portion of the gate electrode overlapped by the drain region can be decreased. Therefore, gate induced drain leakage is reduced, so that off-state leakage current can likewise be greatly reduced.

Abstract translation: 提供了具有低泄漏电流的柱型场效应晶体管。 柱型场效应晶体管包括半导体柱，形成在半导体柱的表面的一部分上的栅极绝缘层，形成在栅极绝缘层上的栅极电极和形成在半导体柱的部分上的源极/漏极区域 其中栅电极不形成，其中栅电极包括第一栅电极，第二栅电极和栅间绝缘层，其中第一栅电极具有比第二栅电极高的功函数 其中，所述栅极绝缘层形成在所述第一栅电极和所述第二栅电极之间，并且所述第一栅电极和所述第二栅电极通过触点或金属互连线电连接。 具有比第一栅极电极功函数低的功函数的第二栅电极的一部分与漏区重叠。 因此，利用具有高功函数的材料形成柱型FET的栅电极，从而可以提高阈值电压，并且可以减小与漏极区重叠的部分栅极的功函数。 因此，栅极感应漏极泄漏减小，从而同样可以大大降低截止状态的漏电流。

公开(公告)号：US20080080642A1

公开(公告)日：2008-04-03

申请号：US11864444

申请日：2007-09-28

Applicant: Jong-Ho LEE ,  Sang-Boh YUN ,  Dae-Young PARK ,  Joo-Hyun LEE

Inventor： Jong-Ho LEE ,  Sang-Boh YUN ,  Dae-Young PARK ,  Joo-Hyun LEE

IPC: H04L27/00

CPC classification number: H04L1/0643 ,  H04B7/0669

Abstract: A data encoding/decoding method in a multiple antenna communication system is provided. In the multiple antenna communication system, a transmitting end includes an encoder for performing Space Time Block Code (STBC) encoding on certain symbols among Transmit (Tx) symbols, a multiplexer for performing spatial multiplexing on the rest of symbols among the Tx symbols, and a transmitter for transmitting the STBC encoded symbols and the spatial-multiplexed symbols through a plurality of antennas.

Abstract translation: 提供了一种多天线通信系统中的数据编码/解码方法。 在多天线通信系统中，发送端包括：编码器，用于对发送（Tx）符号中的某些符号执行空时分组码（STBC）编码;多路复用器，用于对Tx符号之间的其余符号执行空间复用;以及 用于通过多个天线发送STBC编码符号和空间复用符号的发射机。