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21.发明授权
公开(公告)号：US4506340A
公开(公告)日：1985-03-19
申请号：US481684
申请日：1983-04-04
IPC分类号： G06F7/72
CPC分类号： G06F7/722
摘要： Method and apparatus for producing the residue of the product of a multiplier and a multiplicand where the multiplier, multiplicand and product are residues with respect to a check base m, and where m=(2.sup.b -1) and b is the number of bits in a residue. An addressable memory device has at least 2 2(b-1) memory locations with each memory location having an address of 2 (b-1) bits. The address of each memory location can be considered as having two components each of (b-1) bits. The residue stored at each addressable location of the device is the residue of the product of the two components of its address. In response to each address being applied to the memory device, the residue of the product of the two components stored at the addressed memory location is read out of the device. The lower order (b-1) bits of the multiplier is applied to the device if the most significant bit of the multiplier is a logical zero. If the most significant bit of the multiplier is a logical one, the complement of the lower order (b-1) bits is applied and forms one component of the address of a memory location of the device. Similarly, the value of the most significant bit of the multiplicand determines whether the lower order (b-1) bits of the multiplicand or their complements form the other component of the address applied to the memory device. The residue read out of the addressed location is complemented to produce the residue of the product stored at the addressed memory location if and only if one of the most significant bits of the multiplier and multiplicand is a logical one, otherwise the residue read out of the memory device is the residue of the product of the multiplier and the multiplicand.
摘要翻译： 用于产生乘法器和乘法器的乘积残差的方法和装置，其中乘法器，被乘数和乘积相对于校验位m是残差，并且其中m =（2b-1）和b是位数 一个残留物 可寻址存储器件具有至少2 2（b-1）个存储器位置，每个存储器位置具有2（b-1）位的地址。 每个存储器位置的地址可以被认为具有每个（b-1）位的两个分量。 存储在设备的每个可寻址位置的残留物是其地址的两个组件的乘积的残留物。 响应于将每个地址应用于存储器设备，存储在寻址的存储器位置的两个组件的乘积的残差从设备中读出。 如果乘法器的最高有效位为逻辑0，则乘法器的低阶（b-1）位被施加到器件。 如果乘法器的最高有效位是逻辑1，则应用较低阶（b-1）位的补码，并且形成设备的存储器位置的地址的一个分量。 类似地，被乘数的最高有效位的值确定被乘数或其补码的低阶（b-1）位是否构成应用于存储器件的地址的另一分量。 补充了从寻址位置读出的残差，以产生存储在寻址的存储器位置的产品的剩余，如果且仅当乘法器和被乘数中的最高有效位之一是逻辑1，否则从 存储器件是乘法器和被乘数乘积的残差。
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22.发明授权
公开(公告)号：US4151510A
公开(公告)日：1979-04-24
申请号：US900627
申请日：1978-04-27
CPC分类号： H03M13/17
摘要： In an information handling system in which a cyclic code is utilized to both detect and correct errors and a cyclical redundancy code is used for supplementary detection of errors, the cyclical redundancy code (CRC) polynomial is chosen to be a factor of the generator polynomial, g(x), of the error detection and correction (EDAC) code. In this way, the same check bits in the code word used for error detection and correction may be further utilized for a CRC check to supplement the error detection capabilities of the system. The risk of miscorrection of data is reduced to de minimus levels by the partitioning of data and count fields in the course of the development of the error detection and correction codes. Practice of the teachings herein disclosed provides a more efficient error detection and correction system with greatly reduced risk of miscorrection. An embodiment of the invention is disclosed following the methodology taught herein.
摘要翻译： 在利用循环码来检测和纠正错误的信息处理系统中，循环冗余码被用于补充检测错误，循环冗余码（CRC）多项式被选择为生成多项式的因子， g（x），错误检测和校正（EDAC）代码。 以这种方式，用于错误检测和校正的代码字中的相同校验位可以进一步用于CRC校验以补充系统的错误检测能力。 错误检测和校正码开发过程中数据分割和计数字段的数据误差风险降低到最小级别。 本文公开的教导的实践提供了一种更有效的错误检测和校正系统，其大大降低了错误修复的风险。 根据本文教导的方法公开本发明的实施例。
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公开(公告)号：US09729319B2
公开(公告)日：2017-08-08
申请号：US14570611
申请日：2014-12-15
CPC分类号： H04L9/0894 , H04L9/0822 , H04L2209/12
摘要： Methods and systems are disclosed for key management for on-the-fly hardware decryption within an integrated circuit. Encrypted information is received from an external memory and stored in an input buffer within the integrated circuit. The encrypted information includes one or more encrypted key blobs. The encrypted key blobs include one or more secret keys for encrypted code associated with one or more encrypted software images stored within the external memory. A key-encryption key (KEK) code for the encrypted key blobs is received from an internal data storage medium within the integrated circuit, and the KEK code is used to generate one or more key-encryption keys (KEKs). A decryption system then decrypts the encrypted key blobs using the KEKs to obtain the secret keys, and the decryption system decrypts the encrypted code using the secret keys. The resulting decrypted software code is then available for further processing.
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公开(公告)号：US20120246542A1
公开(公告)日：2012-09-27
申请号：US13053962
申请日：2011-03-22
CPC分类号： G06F11/1016 , G11C29/52 , G11C2029/0411
摘要： Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the data and, in response to a read access at the memory address, are employed to check for errors in both the address and the data provided in response to the read access (the read data). The ECC checkbit generation process can result, for particular memory addresses, in checkbits that can incorrectly indicate whether errors are present in the read data. Accordingly, the checkbits can be selectively inverted based on the memory address so that the checkbit pattern will not result in an incorrect error detection or correction.
摘要翻译： 基于要写入的数据（写入数据）和存储器地址的每次对存储器地址的写入生成纠错码（ECC）校验码。 ECC校验位与数据一起存储，并且响应于在存储器地址处的读取访问来检查响应于读取访问（读取数据）提供的地址和数据中的错误。 对于特定的存储器地址，ECC校验位生成过程可能导致错误地指示读取数据中是否存在错误的校验位。 因此，可以基于存储器地址选择性地反转校验位，使得校验位模式不会导致不正确的错误检测或校正。
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公开(公告)号：US20120215989A1
公开(公告)日：2012-08-23
申请号：US13033317
申请日：2011-02-23
IPC分类号： G06F12/14
CPC分类号： G06F12/1416
摘要： A system and method are disclosed for determining whether to allow or deny an access request based upon one or more descriptors at a local memory protection unit and based upon one or more descriptors a system memory protection unit. When multiple descriptors of a memory protection unit apply to a particular request, the least-restrictive descriptor will be selected. System access information is stored at a cache of a local core in response to a cache line being filled. The cached system access information is merged with local access information, wherein the most-restrictive access is selected.
摘要翻译： 公开了一种用于基于本地存储器保护单元上的一个或多个描述符并且基于一个或多个描述符来确定系统存储器保护单元来确定是允许还是拒绝访问请求的系统和方法。 当存储器保护单元的多个描述符适用于特定请求时，将选择最小限制描述符。 响应于正在填充的高速缓存行，将系统访问信息存储在本地核心的高速缓存中。 缓存的系统访问信息与本地访问信息合并，其中选择最严格的访问。
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26.发明授权
公开(公告)号：US5964893A
公开(公告)日：1999-10-12
申请号：US520945
申请日：1995-08-30
CPC分类号： G06F11/364 , G06F11/3648
摘要： A data processor (3) executes a real time trace function which allows an external development system (7) to dynamically observe internal operations of data processor (3) without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the data processor (3). A debug module (10) of data processor (3) provides a parallel output port for providing internal operating information via a DDATA signal and a PST signal. The DDATA signal provides data which reflects operand values and the PST signal provides encoded status information which reflects an execution status of a central processing unit 92). Furthermore, the DDATA signal also provides captured instruction address program flow changes to allow external development system (7) to trace an exact program flow without requiring an externally visible address bus or an externally visible data bus.
摘要翻译： 数据处理器（3）执行实时跟踪功能，其允许外部开发系统（7）动态地观察数据处理器（3）的内部操作，而不假定外部总线的类型或可用性，并且不显着影响效率和速度 的数据处理器（3）。 数据处理器（3）的调试模块（10）提供并行输出端口，用于经由DDATA信号和PST信号提供内部操作信息。 DDATA信号提供反映操作数值的数据，并且PST信号提供反映中央处理单元92的执行状态的编码状态信息）。 此外，DDATA信号还提供捕获的指令地址程序流程更改，以允许外部开发系统（7）跟踪精确的程序流程，而不需要外部可见的地址总线或外部可见的数据总线。
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公开(公告)号：US5765190A
公开(公告)日：1998-06-09
申请号：US629927
申请日：1996-04-12
CPC分类号： G06F12/0864 , G06F12/0837 , G06F12/12
摘要： A most recently used bit (25) is used to determine if a data transfer should occur from a fill buffer (20) into a data memory (32) in a cache (15) If the data to be displaced in the data memory (32) has been referenced more recently than the data present in the fill buffer (20), then the transfer should not occur. When a cache miss does occur, a control register (50) is used to determine the conditions for loading the fill buffer (20).
摘要翻译： 最近使用的位（25）用于确定数据传输是否应当从缓冲器（20）到高速缓存（15）中的数据存储器（32）中发生。如果要在数据存储器（32）中移位的数据 ）比填充缓冲器（20）中存在的数据更近被引用，则不应该发生传输。 当发生高速缓存未命中时，使用控制寄存器（50）来确定用于加载填充缓冲器（20）的条件。
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公开(公告)号：US5704034A
公开(公告)日：1997-12-30
申请号：US520949
申请日：1995-08-30
申请人： Joseph C. Circello
发明人： Joseph C. Circello
CPC分类号： G06F11/364 , G06F11/3648
摘要： A data processor (3) executes a breakpoint operation before an exception processing routine for a reset operation is initiated. When an External Reset signal is asserted and subsequently negated, a window of time exists in which data processor (3) is quiescent before beginning an actual reset exception processing routine. If an external breakpoint signal, BKPT is asserted during a quiescent time by external development system (7), data processor (3) downloads a target memory value into a memory (6) such that any hardware register configuration may be performed.
摘要翻译： 在启动用于复位操作的异常处理程序之前，数据处理器（3）执行断点操作。 当外部复位信号被断言并随后被否定时，存在在开始实际复位异常处理例程之前数据处理器（3）静止的时间窗口。 如果在外部开发系统（7）的静止时间期间外部断点信号+ E，ovs BKPT + EE被断言，则数据处理器（3）将目标存储器值下载到存储器（6）中，使得任何硬件寄存器配置 被执行。
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29.发明授权Zero-cycle multi-state branch cache prediction data processing system and method thereof 失效零周期多状态分支缓存预测数据处理系统及其方法
公开(公告)号：US5592634A
公开(公告)日：1997-01-07
申请号：US242766
申请日：1994-05-16
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A branch cache (40) has a plurality of storage levels (120, 122, 140, and/or 142) wherein at least two write registers (114 and 116) are used to perform a parallel write operation to at least two of the storage levels in the plurality of storage levels (120, 122, 140, and/or 142). The two write registers (114 and 116) are provided due to the fact that the branch cache 40 is implemented as a multi-state (typically five state--see FIG. 5) branch prediction unit having instruction folding. Instruction folding, as taught herein, allows a branch instruction which is predicted as being taken to be executed along with an instruction that precedes the branch in execution flow. The instruction which directly precedes the branch in execution flow is usually the instruction which is used to "fold" the branch. Effectively, this instruction folding allows branches, which are predicted as being taken, to be executed in zero clock cycles.
摘要翻译： 分支高速缓存（40）具有多个存储级别（120,122,140和/或142），其中至少两个写入寄存器（114和116）用于对存储器中的至少两个执行并行写入操作 多个存储级别（120,122,140和/或142）中的级别。 由于分支高速缓存40被实现为具有指令折叠的多状态（通常为五状态 - 图5）分支预测单元的事实，所以提供了两个写入寄存器（114和116）。 如本文所教导的指令折叠允许预测被执行的分支指令与执行流程中的分支之前的指令一起执行。 直接在执行流程中的分支之前的指令通常是用于“折叠”分支的指令。 有效地，该指令折叠允许在零时钟周期中执行被预测为被采取的分支。
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公开(公告)号：US4602368A
公开(公告)日：1986-07-22
申请号：US485551
申请日：1983-04-15
CPC分类号： G06F12/1045
摘要： An associative memory used to translate a virtual page number (VPN) of a virtual word address to a physical page number (PPN) of a physical word address of a random access memory of a digital computer system is provided with a pair of independently addressable validity bit arrays, each of which arrays can store a validity bit in each of the addressable locations of each array. A pointer enables only one of the validity bit arrays to receive address signals corresponding to the lower virtual page number (LVPN) of a VPN. The validity bit read out of the memory location corresponding to the LVPN of the enabled array is used in determining if the PPN read out of the corresponding memory location of the associative memory is valid. The bits of the disabled array, immediately after it is disabled, are all reset, or cleared. After all validity bits of the disabled array are reset, a clear associative memory paging (CAMP) instruction can be executed to invalidate all entries written into the associative memory by enabling the cleared disabled array and disabling the array enabled at the time such a CAMP instruction begins execution.
摘要翻译： 用于将虚拟字地址的虚拟页号（VPN）转换为数字计算机系统的随机存取存储器的物理字地址的物理页号（PPN）的关联存储器具有一对可独立寻址的有效性 位阵列，其中每个阵列可以在每个阵列的每个可寻址位置中存储有效位。 指针仅使一个有效位阵列接收对应于VPN的较低虚拟页号（LVPN）的地址信号。 在确定从关联存储器的相应存储器位置读出的PPN是否有效的情况下，使用从与使能的阵列的LVPN相对应的存储单元中读出的有效位。 禁用阵列的位在其被禁用之后立即被复位或清除。 在禁用阵列的所有有效位被重置之后，可以执行清除关联存储器寻呼（CAMP）指令，以通过启用清除的禁用阵列来禁用写入关联存储器的所有条目，并在此类CAMP指令时禁用启用阵列 开始执行。
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