公开(公告)号：US5912489A

公开(公告)日：1999-06-15

申请号：US940674

申请日：1997-09-30

申请人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

发明人： Pau-Ling Chen ,  Mike Van Buskirk ,  Shane Charles Hollmer ,  Binh Quang Le ,  Shoichi Kawamura ,  Chung-You Hu ,  Yu Sun ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0483

摘要： A series select transistor and a source select transistor are connected in series at the end of a NAND string of floating gate data storage transistors. The floating gates, the series select gate, and the source select gate are all preferably formed of polysilicon. The same tunnel oxide layer is used as gate oxide for the series select transistor and source select transistor as well as for the floating gate data storage transistors. Two layers of polysilicon in the series select gate and the source select gates are tied together. The series select transistor is tied to the last transistor in the NAND string. The source select transistor is tied to the array Vss supply. In order to program inhibit a specific NAND cell during the programming of another NAND cell, the gate of the series select transistor is raised to Vcc, while the gate of the source select transistor is held to ground. The two transistors in series are able to withstand a much higher voltage at the end of the NAND string without causing gated-diode junction or oxide breakdown in either the series or the source select transistor.

摘要翻译： 串联选择晶体管和源选择晶体管串联连接在浮动数据存储晶体管的NAND串的末端。 浮置栅极，串联选择栅极和源选择栅极都优选由多晶硅形成。 相同的隧道氧化物层用作串联选择晶体管和源极选择晶体管以及浮动栅极数据存储晶体管的栅极氧化物。 串联选择栅极和源极选择栅极中的两层多晶硅结合在一起。 串联选择晶体管连接到NAND串中的最后一个晶体管。 源选择晶体管连接到阵列Vss电源。 为了在另一NAND单元的编程期间编程禁止特定NAND单元，串联选择晶体管的栅极升高到Vcc，同时源极选择晶体管的栅极保持接地。 串联的两个晶体管能够在NAND串的末端承受高得多的电压，而不会在串联或源极选择晶体管中产生门极二极管结或氧化物击穿。

公开(公告)号：US07026843B1

公开(公告)日：2006-04-11

申请号：US10759855

申请日：2004-01-16

申请人： Tien-Chun Yang ,  Pau-Ling Chen

发明人： Tien-Chun Yang ,  Pau-Ling Chen

IPC分类号： G01R19/00

CPC分类号： G11C16/26 ,  G11C7/062

摘要： An exemplary cascode amplifier circuit comprises a first intrinsic FET, a second intrinsic FET, a third intrinsic FET, and a fourth FET. The first intrinsic FET has a source connected to a target memory cell via a bit line and a drain connected to a first node. The second intrinsic FET has a gate connected to the source of the first intrinsic FET and a source connected to a reference voltage. The second intrinsic FET also has a drain connected at a second node to a gate of the first intrinsic FET. The third intrinsic FET has a source connected to the first node and a gate connected to a supply voltage, and further provides a load across the supply voltage and the first node. The fourth FET has a source connected to the second node and a drain connected to the supply voltage, the fourth FET having a gate connected to an input control voltage.

摘要翻译： 示例性共源共栅放大器电路包括第一本征FET，第二本征FET，第三本征FET和第四FET。 第一本征FET具有经由位线连接到目标存储器单元的源极和连接到第一节点的漏极。 第二本征FET具有连接到第一本征FET的源极的栅极和连接到参考电压的源极。 第二本征FET还具有在第二节点处连接到第一本征FET的栅极的漏极。 第三本征FET具有连接到第一节点的源极和连接到电源电压的栅极，并且进一步在电源电压和第一节点之间提供负载。 第四FET具有连接到第二节点的源极和连接到电源电压的漏极，第四FET具有连接到输入控制电压的栅极。

公开(公告)号：US06819591B1

公开(公告)日：2004-11-16

申请号：US10762071

申请日：2004-01-20

申请人： Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Santosh Yachareni ,  Pau-Ling Chen

发明人： Kazuhiro Kurihara ,  Ming-Huei Shieh ,  Santosh Yachareni ,  Pau-Ling Chen

IPC分类号： G11C1604

CPC分类号： G11C16/0475 ,  G11C16/0491

摘要： An exemplary memory sector erase method comprises the steps of pre-programming a first bit and a second bit of a plurality of core memory cells of a plurality of memory blocks of a target memory sector, pre-programming one of a third bit and a fourth bit of a first neighboring memory cell adjacent to the target memory sector, and erasing the first bit and the second bit of the plurality of core memory cells of the plurality of memory blocks. According to another embodiment, the method further comprises programming the one of the third bit and the fourth bit of the first neighboring memory cell after the erasing step.

摘要翻译： 示例性存储器扇区擦除方法包括以下步骤：对目标存储器扇区的多个存储器块的多个核心存储器单元的第一位和第二位进行预编程，预编程第三位和第四 与目标存储器扇区相邻的第一相邻存储单元的位，以及擦除多个存储块中的多个存储单元的第一位和第二位。 根据另一实施例，该方法还包括在擦除步骤之后编程第一相邻存储器单元的第三位和第四位之一。

公开(公告)号：US06791880B1

公开(公告)日：2004-09-14

申请号：US10431320

申请日：2003-05-06

申请人： Kazuhiro Kurihara ,  Binh Quang Le ,  Pau-Ling Chen ,  Darlene Hamilton ,  Edward Hsia

发明人： Kazuhiro Kurihara ,  Binh Quang Le ,  Pau-Ling Chen ,  Darlene Hamilton ,  Edward Hsia

IPC分类号： G11C1606

CPC分类号： G11C29/026 ,  G11C16/04 ,  G11C16/349 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5006

摘要： A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.

摘要翻译： 具有可调节电流源以提供寿命终止模拟的非易失性存储器读取电路。 包括用于提供用于与正在读取的存储器单元的电流进行比较的参考电流的参考电流源的闪速存储器件包括与被读取的存储器单元并联的可调电流源，以及与可读电流源并联的可调电流源 参考电流源。 来自存储单元，参考电流源及其并联可调电流源的电流被输入到共源共栅电路，用于转换成由读出放大器比较的电压。 可以通过调节可调电流源来评估级联电路和读出放大器响应于存储器单元和参考电流源的变化的行为，使得在读出放大器的每个输入处的组合电流在老化之后模拟电路的电流 或骑自行车。

公开(公告)号：US06643177B1

公开(公告)日：2003-11-04

申请号：US10349293

申请日：2003-01-21

申请人： Binh Quang Le ,  Pau-Ling Chen

发明人： Binh Quang Le ,  Pau-Ling Chen

IPC分类号： G11C1628

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/0475 ,  G11C16/28 ,  G11C2211/5634

摘要： A method for providing a modified threshold voltage distribution for a dynamic reference array in a flash memory cell array. The dynamic reference array and an associated core memory cell array are programmed using two different programming processes to produce different Vt distributions for the dynamic reference array and the core memory cell array. The dynamic reference array is programmed using a finer program pulse to achieve a smaller distribution width, thus enhancing the read margin for the memory cell array. The finer pulse may be of shorter duration or of smaller amplitude. The finer programming process may be applied to one or more threshold voltage distributions (states) in the memory cell array.

摘要翻译： 一种用于为闪存单元阵列中的动态参考阵列提供修改的阈值电压分布的方法。 使用两个不同的编程过程对动态参考阵列和相关联的核心存储器单元阵列进行编程，以为动态参考阵列和核心存储器单元阵列产生不同的Vt分布。 使用更精细的编程脉冲对动态参考阵列进行编程，以实现更小的分布宽度，从而增强存储单元阵列的读取余量。 较细的脉冲可以具有较短的持续时间或较小的振幅。 更精细的编程过程可以应用于存储单元阵列中的一个或多个阈值电压分布（状态）。

公开(公告)号：US06593606B1

公开(公告)日：2003-07-15

申请号：US09718771

申请日：2000-11-22

申请人： Mark W. Randolph ,  Shane Charles Hollmer ,  Pau-Ling Chen ,  Richard M. Fastow

发明人： Mark W. Randolph ,  Shane Charles Hollmer ,  Pau-Ling Chen ,  Richard M. Fastow

IPC分类号： H01L2973

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： An array of memory cells includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines, wherein M=2, 3, 4, 5, . . . wherein each of the M bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=1, 2, 3, . . . , wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts, and wherein contacts overlying a first bit line are staggered with respect to contacts overlying a second bit line that is adjacent to the first bit line.

摘要翻译： 存储器单元阵列包括通过M字线和M位线的网格互连的多个存储器单元，其中M = 2,3,4,5。 。 。 其中埋设M个位线。 该阵列还包括多个触点，其中，每N个字线N = 1,2,3，形成多个触点中的每一个。 。 。 ，其中所述多个触点中的每一个覆盖所述多个存储单元中的不同的存储单元的栅极。 带子将一个掩埋位线连接到位于多个触点中的一个的栅极，并且其中覆盖第一位线的触点相对于与第一位线相邻的第二位线的触点交错。

公开(公告)号：US06331951B1

公开(公告)日：2001-12-18

申请号：US09717550

申请日：2000-11-21

申请人： Edward V. Bautista, Jr. ,  Darlene G. Hamilton ,  Weng Fook Lee ,  Pau-Ling Chen ,  Keith H. Wong

发明人： Edward V. Bautista, Jr. ,  Darlene G. Hamilton ,  Weng Fook Lee ,  Pau-Ling Chen ,  Keith H. Wong

IPC分类号： G11C1606

CPC分类号： G11C16/344 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/3445

摘要： A method and system are disclosed for verifying memory cell erasure, which may be employed in association with a dual bit memory cell architecture. The method includes selectively verifying proper erasure of one of a first bit of the cell and a second bit of the cell, determining that the dual bit memory cell is properly erased if the first and second bits of the cell are properly erased, and selectively erasing at least one of the first and second bits of the cell if one of the first and second bits is not properly erased. The method may also comprise selectively re-verifying proper erasure of one of the first and second bits after selectively erasing at least one of the first and second bits.

摘要翻译： 公开了用于验证存储器单元擦除的方法和系统，其可以与双位存储器单元架构相关联使用。 该方法包括选择性地验证小区的第一比特和小区的第二比特之一的适当擦除，如果小区的第一和第二比特被正确擦除，则确定双比特存储单元被适当地擦除，并且选择性地擦除 如果第一和第二位之一没有被正确擦除，则单元的第一和第二位中的至少一个位。 该方法还可以包括在选择性地擦除第一和第二比特中的至少一个之后，选择性地重新验证第一和第二比特之一的适当擦除。

公开(公告)号：US06292406B1

公开(公告)日：2001-09-18

申请号：US09609678

申请日：2000-07-03

申请人： Binh Q. Le ,  Pau-Ling Chen

发明人： Binh Q. Le ,  Pau-Ling Chen

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C16/08 ,  G11C16/30

摘要： Control circuitry and a method for generating an accurate boosted wordline voltage for selected memory core cells in a semiconductor memory device during a Read mode of operation is provided. Memory core transistors are provided which have their conduction path being coupled between a power supply voltage and a ground potential. Differential amplifier circuitry is responsive to a boost signal and a reference voltage for generating a select wordline voltage. The select wordline voltage is decreased when the wordline voltage is higher than a desired voltage and is increased when the wordline voltage is lower than the desired voltage. The control gates of the memory core transistors are responsive to the select wordline voltage.

摘要翻译： 提供了控制电路和用于在读操作模式期间为半导体存储器件中的所选择的存储器核心单元产生精确提升的字线电压的方法。 提供存储芯体晶体管，其导通路径耦合在电源电压和地电位之间。 差分放大器电路响应于升压信号和用于产生选择字线电压的参考电压。 当字线电压高于期望电压时，选择字线电压降低，当字线电压低于期望电压时，选择字线电压降低。 存储核心晶体管的控制栅极响应于选择字线电压。

公开(公告)号：US06240020B1

公开(公告)日：2001-05-29

申请号：US09427406

申请日：1999-10-25

申请人： Andrew Yang ,  Shane Hollmer ,  Pau-Ling Chen

发明人： Andrew Yang ,  Shane Hollmer ,  Pau-Ling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/24

摘要： A flash memory device includes an array of core cell blocks and page buffers with supporting input/output circuitry. The flash memory device, in addition, contains a method for shielding the bitline for a precharging scheme in which the bitline line of each page buffer is charged prior to the sensing/evaluation cycle of a particular memory element in each core cell block. The precharging scheme increases the speed of response in retrieving information from each core cell block because the bitline line is charged to a predetermined voltage prior to accessing the bitline. The bitline shielding method increases the speed of response further by shielding the effects of neighboring bitlines from each other during the evaluation cycle. The shielding method includes charging different bitlines to preset voltages and then maintaining the preset voltages on a set of the bitlines over the evaluation cycle. The preset voltages are maintained on those bitlines not connected with memory elements undergoing evaluation. The shielding method also includes grounding a latch contained in page buffers connected with the bitlines of memory elements undergoing evaluation prior to the evaluation cycle.

摘要翻译： 闪存器件包括核心单元块阵列和具有支持输入/输出电路的页缓冲器。 另外，闪速存储器件包含用于屏蔽预充电方案的位线的方法，其中在每个核心单元块中的特定存储器元件的感测/评估周期之前，每个页缓冲器的位线被充电。 预充电方案增加了从每个核心单元块检索信息时的响应速度，因为位线在访问位线之前被充电到预定电压。 位线屏蔽方法通过在评估周期期间屏蔽相邻位线的影响进一步增加响应速度。 屏蔽方法包括将不同的位线充电到预设电压，然后在评估周期内将预设电压保持在一组位线上。 在与正在进行评估的存储器元件未连接的那些位线上保持预设电压。 屏蔽方法还包括将与在评估周期之前进行评估的存储器元件的位线连接的页缓冲器中的锁存器接地。

公开(公告)号：US5844840A

公开(公告)日：1998-12-01

申请号：US914543

申请日：1997-08-19

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Chung-You Hu ,  Narbeh Derhacobian

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Charles Hollmer ,  Chung-You Hu ,  Narbeh Derhacobian

IPC分类号： G11C8/08 ,  G11C16/06

CPC分类号： G11C8/08

摘要： According to an aspect of the embodiments, the block decoder control circuits which drive the pass transistors for the word lines for a flash memory array are driven with a control voltage that is regulated to be one enhancement transistors threshold voltage higher than the highest voltage that is actually driven onto the word lines. According to another aspect of some of the embodiments, the block decoder control circuits are implemented with transistors having a very low threshold voltage. According to yet another aspect of some of the embodiments, a special series connection is used to prevent any leakage current through the block decoder control circuit from the high voltage generating charge pumps which might otherwise result from the use of low threshold voltage transistors. In the special series connection, any leakage current occurs from the supply voltage source rather than from the high voltage generating charge pumps. According to still another aspect of some of the embodiments, a special gate connection applies an intermediate bias voltage higher than a positive supply voltage onto the gates of the unselected block decoder transistors that are connected to a high-voltage. Several embodiments are presented which combine the regulated control voltage aspect and various combinations of the other aspects.

摘要翻译： 根据实施例的一个方面，驱动用于闪存阵列的字线的传输晶体管的块解码器控制电路被控制电压驱动，该控制电压被调节为高于最高电压的一个增强晶体管阈值电压 实际上驱动到字线上。 根据一些实施例的另一方面，块解码器控制电路用具有非常低的阈值电压的晶体管来实现。 根据一些实施例的另一方面，使用特殊的串联连接来防止任何来自块解码器控制电路的泄漏电流与由高阈值电压晶体管使用而产生的高电压产生电荷泵。 在特殊的串联连接中，从电源电压源而不是高压发生电荷泵发生泄漏电流。 根据一些实施例的另一方面，特殊栅极连接将高于正电源电压的中间偏置电压施加到连接到高电压的未选择的块解码器晶体管的栅极上。 提出了组合调节的控制电压方面和其他方面的各种组合的几个实施例。