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公开(公告)号：US20170062346A1
公开(公告)日：2017-03-02
申请号：US15068506
申请日：2016-03-11
IPC分类号： H01L23/532 , H01L21/768 , H01L23/522
CPC分类号： H01L23/53276 , H01L21/76834 , H01L21/76885 , H01L21/76886 , H01L23/5226
摘要： According to one embodiment, a semiconductor device is disclosed. The device includes a graphene layer containing impurities, and including a first region and a second region. The second region has a resistance higher than a resistance of the first region. The second region includes a side surface of an end of the graphene layer. The device further includes a first plug being in contact with the first region.
摘要翻译： 根据一个实施例，公开了一种半导体器件。 该装置包括含有杂质的石墨烯层，并且包括第一区域和第二区域。 第二区域具有高于第一区域的电阻的电阻。 第二区域包括石墨烯层的端部的侧表面。 该装置还包括与第一区域接触的第一插头。
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公开(公告)号：US20160276219A1
公开(公告)日：2016-09-22
申请号：US14841333
申请日：2015-08-31
发明人： Makoto WADA , Yuichi YAMAZAKI , Hisao MIYAZAKI , Akihiro KAJITA , Tatsuro SAITO , Atsunobu ISOBAYASHI , Taishi ISHIKURA , Masayuki KATAGIRI , Tadashi SAKAI
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528
CPC分类号： H01L23/53276 , H01L21/76832 , H01L21/76834 , H01L21/76885
摘要： According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a graphene film on a catalytic layer, removing a part of the graphene film to form an exposed side surface of the graphene film, introducing dopant into the graphene film from the exposed side surface, and forming a graphene interconnect by patterning the graphene film into which the dopant is introduced.
摘要翻译： 根据一个实施方案，一种制造半导体器件的方法，该方法包括在催化剂层上形成石墨烯膜，除去一部分石墨烯膜以形成石墨烯膜的暴露侧表面，将掺杂剂引入到石墨烯膜中 暴露的侧表面，并且通过图案化引入掺杂剂的石墨烯膜来形成石墨烯互连。
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公开(公告)号：US20160268200A1
公开(公告)日：2016-09-15
申请号：US15052377
申请日：2016-02-24
IPC分类号： H01L23/528 , H01L27/115 , H01L21/768 , H01L21/8234 , H01L21/02 , H01L23/532 , H01L21/311
CPC分类号： H01L23/5283 , H01L21/02271 , H01L21/31116 , H01L21/76816 , H01L21/76877 , H01L21/76885 , H01L21/76895 , H01L21/823475 , H01L23/528 , H01L23/53214 , H01L23/53219 , H01L23/53228 , H01L23/53233 , H01L23/53242 , H01L23/53257 , H01L23/53276 , H01L23/5329 , H01L27/115
摘要： A semiconductor device includes a first wiring comprising a first conductive material on a semiconductor layer, a second wiring comprising the first conductive material on the semiconductor layer, a third wiring comprising a second conductive material different from the first conductive material, and an insulation film on the semiconductor layer between the first wiring and the second wiring and between the second wiring and the third wiring. The second wiring is provided on at least two sides of the third wiring, and a mean free path of free electrons in the first conductive material is shorter than a mean free path of free electrons in the second conductive material, or the first conductive material shows quantized conduction and the second conductive material does not show quantized conduction. The first wiring, the second wiring, the third wiring, and the insulation film are in one wiring layer provided on the semiconductor layer.
摘要翻译： 一种半导体器件包括：第一布线，包括半导体层上的第一导电材料;第二布线，包括半导体层上的第一导电材料;第三布线，包括不同于第一导电材料的第二导电材料;以及绝缘膜， 第一布线和第二布线之间以及第二布线和第三布线之间的半导体层。 第二布线设置在第三布线的至少两侧，第一导电材料中的自由电子的平均自由程短于第二导电材料中的自由电子的平均自由程，或第一导电材料显示 量化导电，第二导电材料不显示量子化导电。 第一布线，第二布线，第三布线和绝缘膜位于设置在半导体层上的一个布线层中。
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公开(公告)号：US20150360412A1
公开(公告)日：2015-12-17
申请号：US14476485
申请日：2014-09-03
发明人： Atsunobu ISOBAYASHI
CPC分类号： G03F7/0002
摘要： According to one embodiment, there is provided a template including a first pattern, a second pattern, and a first dummy pattern. A concave-convex pattern having the width equal to 100 nm or less is arranged in the first pattern. A concave-convex pattern having the width wider than 100 nm is arranged in the second pattern. The first dummy pattern is arranged at the bottom of a concave pattern of the second pattern and made shorter than the concave-convex pattern. The first dummy pattern is arranged adjacently to another pattern at an interval equal to 100 nm or less.
摘要翻译： 根据一个实施例，提供了包括第一图案，第二图案和第一虚设图案的模板。 在第一图案中布置具有等于100nm或更小的宽度的凹凸图案。 在第二图案中布置宽度大于100nm的凹凸图案。 第一虚设图形布置在第二图案的凹形图案的底部并且比凹凸图案更短。 第一伪图案以等于100nm或更小的间隔相邻于另一图案布置。
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公开(公告)号：US20150061133A1
公开(公告)日：2015-03-05
申请号：US14176993
申请日：2014-02-10
IPC分类号： H01L23/498
CPC分类号： H01L23/49877 , H01L21/00 , H01L21/76885 , H01L23/53276 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device using a graphene film comprises a catalytic metal layer formed on a groundwork substrate includes a contact via, and a multilayered graphene layer formed in a direction parallel with a surface of the substrate. The catalytic metal layer is formed to be connected to the contact via and covered with an insulation film except one side surface. The multilayered graphene layer is grown from the side surface of the catalytic metal layer which is not covered with the insulation film.
摘要翻译： 根据一个实施例，使用石墨烯薄膜的半导体器件包括形成在基底基板上的催化金属层，其包括接触通孔，以及在与基板的表面平行的方向上形成的多层石墨烯层。 催化金属层形成为连接到接触通孔，并被除了一个侧表面之外的绝缘膜覆盖。 多层石墨烯层从没有被绝缘膜覆盖的催化金属层的侧表面生长。
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公开(公告)号：US20150061131A1
公开(公告)日：2015-03-05
申请号：US14202683
申请日：2014-03-10
发明人： Tatsuro SAITO , Makoto WADA , Atsunobu ISOBAYASHI , Akihiro KAJITA , Hisao MIYAZAKI , Tadashi SAKAI
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76877 , H01L21/28556 , H01L23/5226 , H01L23/53276 , H01L2221/1094 , H01L2924/0002 , Y10S977/754 , Y10S977/932 , H01L2924/00
摘要： According to one embodiment, a semiconductor device in which CNTs are used for a contact via comprises a substrate includes a contact via groove, a catalyst layer for CNT growth which is formed at the bottom of the groove, and a CNT via formed by filling the CNTs into the groove in which the catalyst layer is formed. Each of the CNTs is formed by stacking a plurality of graphene layers in a state in which they are inclined depthwise with respect to the groove, and formed such that ends of the graphene layers are exposed on a sidewall of the CNT. Further, the CNT is doped with at least one element from the sidewall of the CNT.
摘要翻译： 根据一个实施例，其中CNT用于接触通孔的半导体器件包括衬底，其包括接触通孔槽，形成在沟槽底部的用于CNT生长的催化剂层和通过填充 CNT进入形成催化剂层的槽中。 每个CNT通过在它们相对于凹槽深度方向倾斜的状态下堆叠多个石墨烯层而形成，并且形成为使得石墨烯层的端部暴露在CNT的侧壁上。 此外，CNT从CNT的侧壁掺杂有至少一种元素。
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27.发明申请公开(公告)号：US20140252615A1
公开(公告)日：2014-09-11
申请号：US13958155
申请日：2013-08-02
发明人： Tatsuro SAITO , Makoto WADA , Atsunobu ISOBAYASHI
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53276 , H01L21/76831 , H01L21/76844 , H01L21/76846 , H01L21/76876 , H01L21/76879 , H01L23/5226 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a semiconductor device includes a wiring, a first insulation film, an underlayer deactivation layer, an underlayer, a catalyst layer and a carbon nanotube. The first insulation film is formed on the wiring and includes a hole which exposes the wiring. The underlayer deactivation layer is formed on the first insulation film at a side surface of the hole, and exposes the wiring at a bottom surface of the hole. The underlayer is formed on an exposed surface of the wiring at the bottom surface of the hole and on the underlayer deactivation layer at the side surface of the hole. The catalyst layer is formed on the underlayer at the bottom surface and the side surface of the hole. The carbon nanotube extends from the catalyst layer at the bottom surface of the hole, and fills the hole.
摘要翻译： 根据一个实施例，半导体器件包括布线，第一绝缘膜，底层失活层，底层，催化剂层和碳纳米管。 第一绝缘膜形成在布线上，并且包括露出布线的孔。 在该孔的侧面的第一绝缘膜上形成有底层钝化层，使该孔的底面的布线露出。 底层形成在孔底部的布线的露出面上，在孔的侧面的底层钝化层上形成。 催化剂层形成在孔的底面和侧面的底层上。 碳纳米管从孔的底面的催化剂层延伸，填充孔。
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