SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号:US20170062346A1

    公开(公告)日:2017-03-02

    申请号:US15068506

    申请日:2016-03-11

    摘要: According to one embodiment, a semiconductor device is disclosed. The device includes a graphene layer containing impurities, and including a first region and a second region. The second region has a resistance higher than a resistance of the first region. The second region includes a side surface of an end of the graphene layer. The device further includes a first plug being in contact with the first region.

    摘要翻译: 根据一个实施例,公开了一种半导体器件。 该装置包括含有杂质的石墨烯层,并且包括第一区域和第二区域。 第二区域具有高于第一区域的电阻的电阻。 第二区域包括石墨烯层的端部的侧表面。 该装置还包括与第一区域接触的第一插头。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20150061133A1

    公开(公告)日:2015-03-05

    申请号:US14176993

    申请日:2014-02-10

    IPC分类号: H01L23/498

    摘要: According to one embodiment, a semiconductor device using a graphene film comprises a catalytic metal layer formed on a groundwork substrate includes a contact via, and a multilayered graphene layer formed in a direction parallel with a surface of the substrate. The catalytic metal layer is formed to be connected to the contact via and covered with an insulation film except one side surface. The multilayered graphene layer is grown from the side surface of the catalytic metal layer which is not covered with the insulation film.

    摘要翻译: 根据一个实施例,使用石墨烯薄膜的半导体器件包括形成在基底基板上的催化金属层,其包括接触通孔,以及在与基板的表面平行的方向上形成的多层石墨烯层。 催化金属层形成为连接到接触通孔,并被除了一个侧表面之外的绝缘膜覆盖。 多层石墨烯层从没有被绝缘膜覆盖的催化金属层的侧表面生长。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20150061131A1

    公开(公告)日:2015-03-05

    申请号:US14202683

    申请日:2014-03-10

    IPC分类号: H01L23/48 H01L21/768

    摘要: According to one embodiment, a semiconductor device in which CNTs are used for a contact via comprises a substrate includes a contact via groove, a catalyst layer for CNT growth which is formed at the bottom of the groove, and a CNT via formed by filling the CNTs into the groove in which the catalyst layer is formed. Each of the CNTs is formed by stacking a plurality of graphene layers in a state in which they are inclined depthwise with respect to the groove, and formed such that ends of the graphene layers are exposed on a sidewall of the CNT. Further, the CNT is doped with at least one element from the sidewall of the CNT.

    摘要翻译: 根据一个实施例,其中CNT用于接触通孔的半导体器件包括衬底,其包括接触通孔槽,形成在沟槽底部的用于CNT生长的催化剂层和通过填充 CNT进入形成催化剂层的槽中。 每个CNT通过在它们相对于凹槽深度方向倾斜的状态下堆叠多个石墨烯层而形成,并且形成为使得石墨烯层的端部暴露在CNT的侧壁上。 此外,CNT从CNT的侧壁掺杂有至少一种元素。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号:US20160268210A1

    公开(公告)日:2016-09-15

    申请号:US14842545

    申请日:2015-09-01

    IPC分类号: H01L23/532 H01L21/768

    摘要: According to one embodiment, a semiconductor device is disclosed. The device includes interconnects each including a catalyst layer and a graphene layer thereon. The catalyst layer includes a first to fifth catalyst regions arranged along a first direction in order of the first to fifth catalyst regions. The first, third and fifth catalyst regions include upper surfaces higher than those of the second and fourth catalyst regions. Adjacent ones of the first to fifth catalyst regions are in contact with each other. A distance between the first and the third catalyst region and a distance between the third and fifth catalyst region are greater than a mean free path of graphene. The graphene layer includes a first graphene layer on the second catalyst region and a second graphene layer on the fourth catalyst region.

    摘要翻译: 根据一个实施例,公开了一种半导体器件。 该装置包括各自包括催化剂层和其上的石墨烯层的互连。 催化剂层包括按照第一至第五催化剂区域的顺序沿第一方向布置的第一至第五催化剂区域。 第一,第三和第五催化剂区域包括高于第二和第四催化剂区域的上表面。 相邻的第一至第五催化剂区域彼此接触。 第一和第三催化剂区域之间的距离以及第三和第五催化剂区域之间的距离大于石墨烯的平均自由程。 石墨烯层包括第二催化剂区上的第一石墨烯层和第四催化剂区上的第二石墨烯层。

    GRAPHENE WIRING AND METHOD FOR MANUFACTURING THE SAME
    9.
    发明申请
    GRAPHENE WIRING AND METHOD FOR MANUFACTURING THE SAME 有权
    石墨线及其制造方法

    公开(公告)号:US20160086891A1

    公开(公告)日:2016-03-24

    申请号:US14842249

    申请日:2015-09-01

    摘要: Graphene wiring of an embodiment has a graphene intercalation compound including a multilayer graphene having graphene sheets stacked therein and an interlayer substance disposed between layers of the multilayer graphene, and an interlayer cross-linked layer connected to a side surface of the multilayer graphene. The interlayer cross-linked layer has a cross-linked molecular structure including multiple bonded molecules cross-linking the graphene sheets included in the multilayer graphene.

    摘要翻译: 实施例的石墨烯布线具有石墨烯插层化合物,其包括层叠有石墨烯片的多层石墨烯和设置在多层石墨烯的层之间的层间物质,以及连接到多层石墨烯的侧表面的层间交联层。 层间交联层具有包含交联多层石墨烯中所含的石墨烯片的多个键合分子的交联分子结构。