公开(公告)号：US20230253054A1

公开(公告)日：2023-08-10

申请号：US18134719

申请日：2023-04-14

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA ,  Taira SHIBUYA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/32 ,  H10B69/00

Abstract: A semiconductor memory includes a first memory cell configured to be set with a first threshold voltage, the first threshold voltage being one of different threshold voltage levels, a second memory cell configured to be set with a second threshold voltage, the second threshold voltage being one of different threshold voltage levels, a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, and a controller configured to read data of one of different bits based on a combination of the first threshold voltage of the first memory cell and the second threshold voltage of the second memory cell.

公开(公告)号：US20230065159A1

公开(公告)日：2023-03-02

申请号：US17984309

申请日：2022-11-10

Applicant: Kioxia Corporation

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA ,  Masamichi FUJIWARA ,  Kazumasa YAMAMOTO ,  Naoaki KOKUBUN ,  Tatsuro HITOMI ,  Hironori UCHIKAWA

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11 ,  H03M13/37 ,  H03M13/29 ,  H03M13/15

Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

公开(公告)号：US20200211655A1

公开(公告)日：2020-07-02

申请号：US16724100

申请日：2019-12-20

Applicant: KIOXIA CORPORATION

Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA ,  Taira SHIBUYA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  G11C16/34 ,  G06F3/06

Abstract: A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.