公开(公告)号：US11914086B2

公开(公告)日：2024-02-27

申请号：US17666463

申请日：2022-02-07

Applicant: KIOXIA CORPORATION

Inventor： Tomoya Sanuki

IPC: G01T1/24 ,  G01T7/00 ,  G01T1/02 ,  G01T1/16 ,  H10B80/00

CPC classification number: G01T1/244 ,  G01T1/026 ,  G01T1/1606 ,  G01T1/242 ,  G01T1/245 ,  G01T1/247 ,  G01T7/00 ,  H10B80/00

Abstract: A radiation detection device includes a non-volatile memory chip including a plurality of stacked memory cells, and a controller configured to detect gamma rays incident on the non-volatile memory chip during a gamma ray detection window according to a data inversion or a threshold voltage change of at least some of the memory cells in the non-volatile memory chip during the gamma ray detection window.

公开(公告)号：US11862246B2

公开(公告)日：2024-01-02

申请号：US17474904

申请日：2021-09-14

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Yasuhito Yoshimizu ,  Keisuke Nakatsuka ,  Hideto Horii ,  Takashi Maeda

IPC: G11C16/04 ,  G11C16/30 ,  G11C16/32 ,  G11C5/06 ,  G11C16/26 ,  G11C5/02 ,  G11C16/10 ,  G11C16/08

CPC classification number: G11C16/0433 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: A memory system has a memory cell array having a plurality of strings, the plurality of strings each having a plurality of memory cells connected in series, and a controller configured to perform control of transferring charges to be stored in the plurality of memory cells in the string or transferring charges according to stored data, between potential wells of channels in the plurality of memory cells.

公开(公告)号：US11839082B2

公开(公告)日：2023-12-05

申请号：US17396810

申请日：2021-08-09

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  G11C5/06

CPC classification number: H10B43/27 ,  G11C5/063 ,  H01L24/09 ,  H01L25/0657

Abstract: In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.

公开(公告)号：US11579796B2

公开(公告)日：2023-02-14

申请号：US17197667

申请日：2021-03-10

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Yuta Aiba ,  Hitomi Tanaka ,  Masayuki Miura ,  Mie Matsuo ,  Toshio Fujisawa ,  Takashi Maeda

IPC: G06F3/00 ,  G06F3/06

Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of −40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of −40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

公开(公告)号：US11227857B2

公开(公告)日：2022-01-18

申请号：US16809739

申请日：2020-03-05

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Masayoshi Tagami

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: In one embodiment, a semiconductor device includes a substrate, a plurality of transistors provided on the substrate. The device further includes a first interconnect layer provided above the transistors and electrically connected to at least one of the transistors, one or more first plugs provided on the first interconnect layer, and a first pad provided on the first plugs. The device further includes a second pad provided on the first pad, one or more second plugs provided on the second pad, and a second interconnect layer provided on the second plugs. The device further includes a memory cell array provided above the second interconnect layer and electrically connected to the second interconnect layer. A number of the second plugs on the second pad is larger than a number of the first plugs under the first pad.

公开(公告)号：US20210082880A1

公开(公告)日：2021-03-18

申请号：US16809739

申请日：2020-03-05

Applicant: Kioxia Corporation

Inventor： Tomoya Sanuki ,  Masayoshi Tagami

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: In one embodiment, a semiconductor device includes a substrate, a plurality of transistors provided on the substrate. The device further includes a first interconnect layer provided above the transistors and electrically connected to at least one of the transistors, one or more first plugs provided on the first interconnect layer, and a first pad provided on the first plugs. The device further includes a second pad provided on the first pad, one or more second plugs provided on the second pad, and a second interconnect layer provided on the second plugs. The device further includes a memory cell array provided above the second interconnect layer and electrically connected to the second interconnect layer. A number of the second plugs on the second pad is larger than a number of the first plugs under the first pad.