System and method for high reliability fast raid soft decoding for NAND flash memories

    公开(公告)号:US11258466B1

    公开(公告)日:2022-02-22

    申请号:US16819025

    申请日:2020-03-13

    Abstract: A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate first soft information of the first codeword. The circuit may be further configured to generate second soft information of a second codeword. The circuit may be configured to generate third soft information based on the first soft information and the second soft information. The circuit may be configured to decode the result of the read operation on the flash memory using the third soft information.

    Codeword concatenation for correcting errors in data storage devices

    公开(公告)号:US11258464B1

    公开(公告)日:2022-02-22

    申请号:US16844725

    申请日:2020-04-09

    Abstract: Various implementations described herein relate to systems and methods for encoding and decoding data having input payload stored in a non-volatile storage device, including encoding the input payload by concatenating a plurality of short codewords to generate a plurality of encoded short codewords, and decoding the plurality of encoded short codewords to obtain the data, where each of the plurality of short codewords corresponding to a portion of the input payload.

    EFFICIENT DECODING SCHEMES FOR ERROR CORRECTING CODES FOR MEMORY DEVICES

    公开(公告)号:US20250007537A1

    公开(公告)日:2025-01-02

    申请号:US18887114

    申请日:2024-09-17

    Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.

    DEEP NEURAL NETWORK IMPLEMENTATION FOR SOFT DECODING OF BCH CODE

    公开(公告)号:US20240385928A1

    公开(公告)日:2024-11-21

    申请号:US18787270

    申请日:2024-07-29

    Abstract: Systems, methods, non-transitory computer-readable media to perform operations associated with the storage medium. One system includes a storage medium and an encoding/decoding (ED) system to perform operations associated with the storage medium, the ED system being configured to process a set of log-likelihood ratios (LLRs) and a syndrome vector to obtain a set of confidence values for each bit of a codeword, estimate an error vector based on selecting one or more bit locations with confidence values from the set of confidence values above threshold value and applying hard decision decoding to the selected one or more bit locations, calculate a sum LLR score for the estimated error vector, and output a decoded codeword based on the estimated error vector and the sum LLR score.

    FEATURE BASED READ THRESHOLD ESTIMATION IN NAND FLASH MEMORY

    公开(公告)号:US20240312528A1

    公开(公告)日:2024-09-19

    申请号:US18122758

    申请日:2023-03-17

    CPC classification number: G11C16/26 G11C11/54 G11C16/349

    Abstract: A method for reading data from a solid-state drive (SSD) configured to store data in a plurality of memory cells arranged in memory blocks comprising rows, the method performed by a controller in communication with the plurality of memory cells. The method comprises retrieving data from a target row of memory cells of the plurality of memory cells associated with a read request received from a host using initial threshold voltages. The method also includes decoding the data using a hard decision stage. Additionally the method comprises estimating read threshold voltages of the target row of memory cells based on a transformation of a distribution of threshold voltages of cells in a memory block containing the target row when the hard decision decoding stage fails. The method further includes retrieving data from the target row using the estimated read threshold voltages.

    METHOD AND SYSTEM FOR ERROR CORRECTION IN MEMORY DEVICES USING IRREGULAR ERROR CORRECTION CODE COMPONENTS

    公开(公告)号:US20230336190A1

    公开(公告)日:2023-10-19

    申请号:US18341041

    申请日:2023-06-26

    CPC classification number: H03M13/118 H03M13/2909

    Abstract: Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.

    SOFT ERROR DETECTION AND CORRECTION FOR DATA STORAGE DEVICES

    公开(公告)号:US20230305925A1

    公开(公告)日:2023-09-28

    申请号:US18325370

    申请日:2023-05-30

    CPC classification number: G06F11/1068 H03M13/2906 G06F11/1004

    Abstract: Various implementations described herein relate to systems and methods for detecting soft errors, including but not limited to, errors introduced after reading a codeword from a non-volatile memory, and before providing data to a host. Embodiments can include decoding the codeword from the non-volatile memory to obtain at least input data, and determining validity of the input data using a first signature after processing the input data through a data path. If it is determined that the input data is valid using the first signature, the input data is sent to a host.

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