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公开(公告)号：US20230253985A1
公开(公告)日：2023-08-10
申请号：US17586290
申请日：2022-01-27
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Zion Nahisi , Ofir Kanter , Amir Nassie , Hanan Weingarten
CPC classification number: H03M13/1128 , H03M13/152 , H03M13/1108 , H03M13/1125
Abstract: A system for decoding data stored in a non-volatile storage device may include processing circuits configured to decode, in a first iteration, each of a plurality of component codes corresponding to the data by performing a first number of enumerations over hypotheses. The processing circuits may be configured to determine, in the first iteration, an extrinsic value output for each of the component codes based on log-likelihood ratios (LLRs) of one or more error bits of a codeword. The processing circuits may be configured to determine a second number of enumerations based on the extrinsic value. The processing circuits may be configured to decode, in a second iteration, each of the plurality of component codes by performing the second number of enumerations over hypotheses.
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公开(公告)号：US11563450B1
公开(公告)日：2023-01-24
申请号：US16818969
申请日：2020-03-13
Applicant: KIOXIA Corporation
Inventor： Ofir Kanter , Avi Steiner , Hanan Weingarten
Abstract: A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate an estimated codeword based on a result of hard decoding the first codeword and a result of hard decoding a second codeword. The circuit may be further configured to generate soft information based on the hard decoding result of the first codeword and the estimated codeword. The circuit may be further configured to decode the result of the read operation on the flash memory using the soft information.
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公开(公告)号：US11513894B2
公开(公告)日：2022-11-29
申请号：US17135722
申请日：2020-12-28
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Amir Nassie , Anat Rot , Ofir Kanter , Hanan Weingarten
Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.
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公开(公告)号：US20220229725A1
公开(公告)日：2022-07-21
申请号：US17154661
申请日：2021-01-21
Applicant: Kioxia Corporation
Inventor： Ofir Kanter , Avi Steiner , Yasuhiko Kurosawa
Abstract: Various implementations described herein relate to systems and methods for detecting soft errors, including but not limited to, reading a codeword from a non-volatile memory, decoding the codeword to obtain at least input data, determining validity of the input data using a first signature after processing the input data through a data path, and in response to determining that the input data is valid using the first signature, sending the input data to a host.
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25.发明授权公开(公告)号：US12283972B2
公开(公告)日：2025-04-22
申请号：US18341041
申请日：2023-06-26
Applicant: Kioxia Corporation
Inventor： Ofir Kanter , Avi Steiner , Amir Nassie , Hanan Weingarten
Abstract: Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.
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Patent Agency Ranking
公开(公告)号：US12260129B2
公开(公告)日：2025-03-25
申请号：US18124407
申请日：2023-03-21
Applicant: Kioxia Corporation
Inventor： Ofir Kanter , Avi Steiner
Abstract: Disclosed herein are related to a system and a method for adjusting a read voltage threshold to read data from a plurality of memory dies of a nonvolatile memory device. Each of the plurality of memory dies comprises a plurality of blocks. A controller in communication with the plurality of memory dies may read, from a first block of the plurality of blocks, data corresponding to a read command received from a host. The controller may determine a bit error rate for the first block based on the data. The controller may update the read voltage threshold for the first block when the bit error rate for the first block exceeds a first error threshold. The read voltage threshold may be stored in the controller.
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公开(公告)号：US12210412B2
公开(公告)日：2025-01-28
申请号：US18070056
申请日：2022-11-28
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Amir Nassie , Anat Rot , Ofir Kanter , Hanan Weingarten
Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.
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公开(公告)号：US20240313806A1
公开(公告)日：2024-09-19
申请号：US18184916
申请日：2023-03-16
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Ofir Kanter , Hanan Weingarten , Assaf Sella , Nimrod Bregman , Yasuhiko Kurosawa
CPC classification number: H03M13/2909 , H03M13/1105
Abstract: Systems, methods, non-transitory computer-readable media configured to perform operations associated with a storage medium. One system includes the storage medium and an encoding/decoding (ED) system, the ED system being configured to receive a set of input log-likelihood ratios (LLRs) of a component of the plurality of components, determine an extrinsic estimation function based on a set of features of the set of input LLRs, analyze the extrinsic estimation function to obtain a plurality of extrinsic LLR values, map the plurality of extrinsic LLR values to an input LLR of the set of input LLRs, and output, for each component, a plurality of updated LLR values based on the mapping.
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公开(公告)号：US20230307037A1
公开(公告)日：2023-09-28
申请号：US17703199
申请日：2022-03-24
Applicant: Kioxia Corporation
Inventor： Nimrod Bregman , Ofir Kanter
IPC: G11C11/4099 , G11C11/4096 , G11C11/54 , G06K9/62
CPC classification number: G11C11/4099 , G11C11/4096 , G11C11/54 , G06K9/6215 , G06K9/6256
Abstract: A flash memory system may include a flash memory and a circuit for performing operations on the flash memory. The circuit may be configured to obtain reference voltages from one or more read samples, and a plurality of sets of reference voltages. The circuit may be configured to obtain a plurality of distances, each being a distance between a point corresponding to the obtained reference voltages and a point corresponding to a respective set of reference voltages. The circuit may be configured to determine a first set of reference voltages such that a distance between the point corresponding to the obtained reference voltages and a point corresponding to the first set of reference voltage is a minimum distance of the plurality of distances. The circuit may be configured to perform read operations on locations of the flash memory with the first set of reference voltages.
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公开(公告)号：US11734107B2
公开(公告)日：2023-08-22
申请号：US16355555
申请日：2019-03-15
Applicant: Kioxia Corporation
Inventor： Avi Steiner , Hanan Weingarten , Meir Nadam-Olegnowicz , Ofir Kanter , Amir Nassie
CPC classification number: G06F11/1068 , G06F11/004 , G06F11/1028 , G11C29/781 , G11C29/844
Abstract: Various implementations described herein relate to systems and methods for performing error correction in a flash memory device by determining suggested corrections by decoding a codeword. In addition, whether a first set of the suggested corrections obtained based on a first component code of the plurality of component codes agree with a second set of the suggested corrections obtained based on a second component code of the plurality of component codes is determined. One of accepting the first set of the suggested corrections or rejecting the first set of the suggested corrections is selected based on whether the first set of the suggested corrections and the second set of the suggested corrections agree.
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