公开(公告)号：US20080153274A1

公开(公告)日：2008-06-26

申请号：US11646157

申请日：2006-12-26

申请人： Timothy Thurgate ,  Yi He ,  Ming-Sang Kwan ,  Zhizheng Liu ,  Xuguang Wang

发明人： Timothy Thurgate ,  Yi He ,  Ming-Sang Kwan ,  Zhizheng Liu ,  Xuguang Wang

IPC分类号： H01L21/425 ,  G11C11/34

CPC分类号： H01L27/11568 ,  G11C5/02 ,  G11C5/06 ,  H01L27/115

摘要： A method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising performing front end processing, performing a first bitline implant, or pocket implants, or both into the first bitline spacings to establish buried first bitlines within the substrate, depositing a layer of the spacer material over the charge trapping dielectric and the polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the polysilicon layer features to define second bitline spacings between adjacent memory cells, performing a deep arsenic implant into the second bitline spacings to establish a second bitline within the structure that is deeper than the first bit line, removing the sidewall spacers and performing back end processing.

摘要翻译： 一种在半导体衬底上形成双位存储器核心阵列的至少一部分的方法，所述方法包括执行前端处理，执行第一位线注入或袋式注入或二者进入第一位线间隔以建立掩埋的第一位线 在衬底内，在电荷俘获电介质和多晶硅层特征之上沉积间隔物材料层，形成与电荷俘获电介质相邻的侧壁隔离层和多晶硅层特征以限定相邻存储器单元之间的第二位线间隔，执行深度 砷注入到第二位线间隔中，以在结构内建立比第一位线更深的第二位线，去除侧壁间隔件并执行后端处理。

公开(公告)号：US20080037330A1

公开(公告)日：2008-02-14

申请号：US11497597

申请日：2006-08-02

申请人： Sheung-Hee Park ,  Gwyn Jones ,  Wing Leung ,  Edward Franklin Runnion ,  Ming-Sang Kwan ,  Xuguang Wang ,  Yi He

发明人： Sheung-Hee Park ,  Gwyn Jones ,  Wing Leung ,  Edward Franklin Runnion ,  Ming-Sang Kwan ,  Xuguang Wang ,  Yi He

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/344 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/16 ,  G11C16/3445

摘要： A method of erasing a block of flash memory cells by applying a ramped gate erase voltage to the block of memory cells. When an erase verify of the block of memory cells indicates that erasure has not been successfully completed another erase voltage with a greater absolute value than the initial erase voltage can be applied to the block of memory cells until erasure is complete.

摘要翻译： 一种通过向存储器单元块施加斜坡栅极擦除电压来擦除闪存单元块的方法。 当存储器单元块的擦除验证指示擦除尚未成功完成时，具有比初始擦除电压更大的绝对值的另一个擦除电压可以被施加到存储器单元块，直到擦除完成。

公开(公告)号：US20070029604A1

公开(公告)日：2007-02-08

申请号：US11546688

申请日：2006-10-12

申请人： Ning Cheng ,  Minh Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela Hui ,  Yi He ,  Brian Mooney ,  Joan Yang ,  Mark Ramsbey

发明人： Ning Cheng ,  Minh Ngo ,  Hirokazu Tokuno ,  Lu You ,  Angela Hui ,  Yi He ,  Brian Mooney ,  Joan Yang ,  Mark Ramsbey

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11568

摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.

摘要翻译： 本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。 使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。 本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。 相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。 此外，本发明包括前述的未掺杂的TEOS衬垫。

公开(公告)号：US20060291282A1

公开(公告)日：2006-12-28

申请号：US11511763

申请日：2006-08-29

申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

IPC分类号： G11C11/34

CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

公开(公告)号：US20060268593A1

公开(公告)日：2006-11-30

申请号：US11136981

申请日：2005-05-25

申请人： Meng Ding ,  Zhizheng Liu ,  Yi He ,  Mark Randolph

发明人： Meng Ding ,  Zhizheng Liu ,  Yi He ,  Mark Randolph

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/118

摘要： According to one exemplary embodiment, a programmable ROM array includes at least one bitline situated in a substrate. The programmable ROM array further includes at least one wordline situated over the at least one bitline. The programmable ROM array further includes a memory cell situated at an intersection of the at least one bitline and the at least one wordline, where the memory cell includes a dielectric region situated between the at least one bitline and the at least one wordline. A programming operation causes the memory cell to change from a first logic state to a second logic state by causing the dielectric region to break down. The programming operation causes the memory cell to operate as a diode. A resistance of the memory cell can be measured in a read operation to determine if the memory cell has the first or second logic state.

摘要翻译： 根据一个示例性实施例，可编程ROM阵列包括位于衬底中的至少一个位线。 可编程ROM阵列还包括位于至少一个位线上的至少一个字线。 可编程ROM阵列还包括位于所述至少一个位线和所述至少一个字线的交叉点处的存储器单元，其中所述存储器单元包括位于所述至少一个位线和所述至少一个字线之间的电介质区域。 通过使介电区域分解，编程操作使存储单元从第一逻辑状态变为第二逻辑状态。 编程操作使存储单元作为二极管工作。 可以在读取操作中测量存储器单元的电阻，以确定存储单元是否具有第一或第二逻辑状态。

公开(公告)号：US07120063B1

公开(公告)日：2006-10-10

申请号：US10841850

申请日：2004-05-07

申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

摘要翻译： 提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。 可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。 电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。 可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池 ，其中栅极电压电位高于衬底电压电位。

公开(公告)号：US07058540B2

公开(公告)日：2006-06-06

申请号：US10737050

申请日：2003-12-15

申请人： Yi He ,  Gerald J. Ringel ,  Howard E. Hilton ,  Brian Barton

发明人： Yi He ,  Gerald J. Ringel ,  Howard E. Hilton ,  Brian Barton

IPC分类号： G06F15/00 ,  G06F7/38

CPC分类号： G06F17/18 ,  G01R21/133

摘要： Data values representing the (I2+Q2) values are converted to floating-point representations and a histogram of the floating-point numbers is generated. The count for each histogram bin in the histogram is stored in a memory. Each floating-point number acts as an address for a corresponding histogram bin in the memory. The accumulated counts in the histogram bins are then grouped into a desired number of CCDF bins, and the CCDF curve is derived from the histogram data. Grouping the histogram bins into the CCDF bins may include combining one or more histogram bins into a single CCDF bin. Linear interpolation is used to divide a count value in a histogram bin between two CCDF bins when the histogram bin does not align with a single CCDF bin.

摘要翻译： 表示（I＆lt; 2＆gt; +＆lt; 2＆gt; 2）值的数据值被转换为浮点表示，并且生成浮点数的直方图。 直方图中每个直方图单元格的计数都存储在存储器中。 每个浮点数作为存储器中对应的直方图bin的地址。 然后将直方图区块中的累积计数分组为所需数量的CCDF仓，并且从直方图数据导出CCDF曲线。 将直方图箱分组到CCDF箱中可以包括将一个或多个直方图箱组合成单个CCDF箱。 线性插值用于在直方图单元不与单个CCDF模块对齐时，在两个CCDF模块之间的直方图存储区中计算计数值。

公开(公告)号：US06967873B2

公开(公告)日：2005-11-22

申请号：US10677790

申请日：2003-10-02

申请人： Darlene G. Hamilton ,  Zhizheng Liu ,  Mark W. Randolph ,  Yi He ,  Edward Hsia ,  Kulachet Tanpairoj ,  Mimi Lee ,  Alykhan Madhani

发明人： Darlene G. Hamilton ,  Zhizheng Liu ,  Mark W. Randolph ,  Yi He ,  Edward Hsia ,  Kulachet Tanpairoj ,  Mimi Lee ,  Alykhan Madhani

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3404 ,  G11C16/0475 ,  G11C16/107 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345

摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

公开(公告)号：US06958272B2

公开(公告)日：2005-10-25

申请号：US10755740

申请日：2004-01-12

申请人： Emmanuil H. Lingunis ,  Nga-Ching Alan Wong ,  Sameer Haddad ,  Mark W. Randolph ,  Mark T. Ramsbey ,  Ashot Melik-Martirosian ,  Edward F. Runnion ,  Yi He

发明人： Emmanuil H. Lingunis ,  Nga-Ching Alan Wong ,  Sameer Haddad ,  Mark W. Randolph ,  Mark T. Ramsbey ,  Ashot Melik-Martirosian ,  Edward F. Runnion ,  Yi He

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

摘要翻译： 公开了一种用于形成双位存储器核心的阵列的至少一部分的技术。 最初，电荷俘获电介质层的一部分形成在衬底上，并且在电荷俘获电介质层的部分上形成抗蚀剂。 抗蚀剂被图案化，并且以一定角度执行凹穴注入以在衬底内建立口袋植入物。 然后执行位线注入以在衬底内建立掩埋位线。 然后去除图案化的抗蚀剂，并形成剩余的电荷捕获介电层。 在剩余的电荷俘获电介质层中形成字线材料，并且被图案化以形成覆盖在位线上的字线。 口袋种植体用于缓解由半导体尺度缩小引起的互补位干扰（CBD）。 因此，可以使半导体器件更小，并且可以通过本文所阐述的发明概念来实现增加的封装密度。

公开(公告)号：US20050153508A1

公开(公告)日：2005-07-14

申请号：US10755740

申请日：2004-01-12

申请人： Emmanuil Lingunis ,  Nga-Ching Wong ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Ashot Melik-Martirosian ,  Edward Runnion ,  Yi He

发明人： Emmanuil Lingunis ,  Nga-Ching Wong ,  Sameer Haddad ,  Mark Randolph ,  Mark Ramsbey ,  Ashot Melik-Martirosian ,  Edward Runnion ,  Yi He

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/10 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/1083 ,  H01L29/66833 ,  Y10S438/959

摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.