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    Pre-charge method for reading a non-volatile memory cell
    4.
    发明授权
    Pre-charge method for reading a non-volatile memory cell 失效
    用于读取非易失性存储单元的预充电方法

    公开(公告)号：US06788583B2

    公开(公告)日：2004-09-07

    申请号：US10307749

    申请日：2002-12-02

    申请人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

    发明人： Yi He ,  Edward F. Runnion ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Pauling Chen ,  Binh Le

    IPC分类号： G11C1606

    CPC分类号： G11C7/12 ,  G11C16/0475 ,  G11C16/24

    摘要： A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises grounding a first bit line that forms a source junction with a channel region of the first memory cell. A high voltage is applied to a gate of the first memory cell and to a second bit line that is the next bit line to the right of the first bit line and separated from the first bit line only by the channel region. A third bit line, that is the next bit line to the right of the second bit line, is isolated such that its potential is effected only by its junctions with the a second channel region and a third channel region on opposing sides of the third bit line. A high voltage is applied to a pre-charge bit line that is to the right of the third bit line and current flow is detected at the second bit line to determine the programmed status of a source bit of the memory cell.

    摘要翻译： 一种检测存储在双位介质存储器单元阵列内的第一双位介质存储单元的电荷存储区域上的电荷的方法包括使与第一存储单元的沟道区形成源极结的第一位线接地。 高电压被施加到第一存储单元的栅极和第二位线，第二位线是第一位线右侧的下一个位线，并且仅与通道区域从第一位线分离。 位于第二位线右侧的下一个位线的第三位线是隔离的，使得其电位仅由其与第二通道区域的结和仅在第三位的相对侧上的第三通道区域 线。 将高电压施加到位于第三位线右侧的预充电位线，并且在第二位线处检测电流以确定存储器单元的源位的编程状态。

    Method of protecting a memory array from charge damage during fabrication
    5.
    发明授权
    Method of protecting a memory array from charge damage during fabrication 有权
    在制造期间保护存储器阵列免受电荷损伤的方法

    公开(公告)号：US06897110B1

    公开(公告)日：2005-05-24

    申请号：US10305750

    申请日：2002-11-26

    申请人： Yi He ,  Wei Zheng ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Ken Tanpairoj

    发明人： Yi He ,  Wei Zheng ,  Zhizheng Liu ,  Mark W. Randolph ,  Darlene G. Hamilton ,  Ken Tanpairoj

    IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L23/525

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a memory array, while protecting it from charge damage. Bitlines that may have source/drain regions of memory cells are formed in a substrate. Wordlines are formed above the bitlines and may have gate regions. Next, a first metal region that is coupled to one of the bitlines is formed above the bitlines. A second metal region that is not electrically coupled to the first metal region is formed. Then, the first metal region is electrically coupled to the second metal region. Charge damage is reduced by keeping the antenna ratio between the first metal region and the bitline low. For further protection, a diode or fuse may also be formed between the substrate and the portion of the metal region that is coupled to the bitline. Also, fuse may be formed between a bitline and a wordline to protect the wordline.

    摘要翻译： 一种制造存储器阵列的方法，同时保护其免受电荷损坏。 可以在衬底中形成可能具有存储器单元的源极/漏极区的位线。 字线形成在位线之上，并且可以具有栅极区域。 接下来，在位线之上形成耦合到位线之一的第一金属区域。 形成不与第一金属区电耦合的第二金属区域。 然后，第一金属区域电耦合到第二金属区域。 通过保持第一金属区域和位线之间的天线比率降低来减少电荷损坏。 为了进一步的保护，还可以在衬底和耦合到位线的金属区域的部分之间形成二极管或保险丝。 此外，可以在位线和字线之间形成保险丝，以保护字线。

    Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array
    7.
    发明授权
    Method for reading a non-volatile memory cell adjacent to an inactive region of a non-volatile memory cell array 有权
    用于读取与非易失性存储单元阵列的非活动区域相邻的非易失性存储单元的方法

    公开(公告)号：US06771545B1

    公开(公告)日：2004-08-03

    申请号：US10353558

    申请日：2003-01-29

    申请人： Edward Hsia ,  Eric Ajimine ,  Darlene G. Hamilton ,  Pauling Chen ,  Ming-Huei Shieh ,  Mark W. Randolph ,  Edward Runnion ,  Yi He

    发明人： Edward Hsia ,  Eric Ajimine ,  Darlene G. Hamilton ,  Pauling Chen ,  Ming-Huei Shieh ,  Mark W. Randolph ,  Edward Runnion ,  Yi He

    IPC分类号： G11C1604

    CPC分类号： G11C29/82 ,  G11C16/0491 ,  G11C16/3404

    摘要： An array of non-volatile memory cells includes active columns of cells wherein a data pattern may be stored adjacent to damaged or inactive columns wherein data is not stored. A method of storing a data pattern and reproducing the data pattern within such an array comprises storing a charge within a selected plurality of the memory cells within the active column. The selected plurality of memory cells represents a portion of the data pattern. An inactive memory cell programming pattern is identified. The inactive memory cell programming pattern identifies all, or a selected plurality, of the memory cells in the inactive column in which a charge is to be stored for the purpose of periodically storing a charge in the memory cells first inactive column to prevent over erasure, during bulk erase, and leakage from the inactive cells to adjacent active cells. A charge is stored on the selected plurality of the memory cells in the first inactive column. The data pattern is reproduced reading each memory cell within the first active column.

    摘要翻译： 非易失性存储器单元的阵列包括有效的单元格列，其中数据模式可以存储在与不存储数据的损坏或非活动列相邻的位置。 存储数据模式并在其中再现数据模式的方法包括将电荷存储在活动列内的所选择的多个存储单元内。 所选择的多个存储单元表示数据模式的一部分。 识别非活动存储器单元编程模式。 非活动存储器单元编程模式识别要在其中存储电荷的所述非活动列中的所有或选定的多个存储单元，以便在存储单元的第一非活动列中周期性地存储电荷以防止过度擦除， 在批量擦除期间以及从非活性电池泄漏到相邻的活性电池。 在第一非活动列中的所选择的多个存储器单元上存储电荷。 读取在第一活动列内的每个存储单元的数据模式。

    System for programming a non-volatile memory cell
    10.
    发明授权
    System for programming a non-volatile memory cell 有权
    用于编程非易失性存储单元的系统

    公开(公告)号：US06795342B1

    公开(公告)日：2004-09-21

    申请号：US10307667

    申请日：2002-12-02

    申请人： Yi He ,  Zhizheng Liu ,  Mark W. Randolph ,  Sameer S. Haddad

    发明人： Yi He ,  Zhizheng Liu ,  Mark W. Randolph ,  Sameer S. Haddad

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C16/0475 ,  G11C16/0491

    摘要： A system for programming a charge stored on a charge storage region of a dielectric charge trapping layer of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a positive source programming bias to a first bit line that is the source of the selected memory cell while applying a drain programming voltage to a second bit line that forms a drain junction with the channel region and while applying a positive voltage to a selected word line. The source voltage may be applied by coupling the source bit line to a voltage divider or by coupling the source bit line to a resistor which in turn is coupled to a ground. A negative programming bias may also be applied to the substrate and to unselected word lines.

    摘要翻译： 一种用于对存储在双位介质存储器单元阵列内的第一双位介质存储单元的介电电荷俘获层的电荷存储区域上的电荷进行编程的系统包括将正源编程偏置施加到第一位线 同时将漏极编程电压施加到与沟道区形成漏极结的第二位线以及向所选择的字线施加正电压的所选存储单元的源极。 可以通过将源极线耦合到分压器或通过将源极线耦合到电阻器来施加源极电压，电阻器又连接到地电位器。 负编程偏置也可以应用于衬底和未选择的字线。