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    Read-only memory array with dielectric breakdown programmability
    1.
    发明申请
    Read-only memory array with dielectric breakdown programmability 审中-公开
    具有介电击穿可编程性的只读存储阵列

    公开(公告)号：US20060268593A1

    公开(公告)日：2006-11-30

    申请号：US11136981

    申请日：2005-05-25

    申请人： Meng Ding ,  Zhizheng Liu ,  Yi He ,  Mark Randolph

    发明人： Meng Ding ,  Zhizheng Liu ,  Yi He ,  Mark Randolph

    IPC分类号： G11C17/00

    CPC分类号： G11C17/16 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/118

    摘要： According to one exemplary embodiment, a programmable ROM array includes at least one bitline situated in a substrate. The programmable ROM array further includes at least one wordline situated over the at least one bitline. The programmable ROM array further includes a memory cell situated at an intersection of the at least one bitline and the at least one wordline, where the memory cell includes a dielectric region situated between the at least one bitline and the at least one wordline. A programming operation causes the memory cell to change from a first logic state to a second logic state by causing the dielectric region to break down. The programming operation causes the memory cell to operate as a diode. A resistance of the memory cell can be measured in a read operation to determine if the memory cell has the first or second logic state.

    摘要翻译： 根据一个示例性实施例，可编程ROM阵列包括位于衬底中的至少一个位线。 可编程ROM阵列还包括位于至少一个位线上的至少一个字线。 可编程ROM阵列还包括位于所述至少一个位线和所述至少一个字线的交叉点处的存储器单元，其中所述存储器单元包括位于所述至少一个位线和所述至少一个字线之间的电介质区域。 通过使介电区域分解，编程操作使存储单元从第一逻辑状态变为第二逻辑状态。 编程操作使存储单元作为二极管工作。 可以在读取操作中测量存储器单元的电阻，以确定存储单元是否具有第一或第二逻辑状态。

    Back-to-back NPN/PNP protection diodes
    4.
    发明授权
    Back-to-back NPN/PNP protection diodes 有权
    背对背NPN / PNP保护二极管

    公开(公告)号：US07573103B1

    公开(公告)日：2009-08-11

    申请号：US11855704

    申请日：2007-09-14

    申请人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

    发明人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0266 ,  H01L27/0255

    摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN diode includes a p-type substrate connected to ground, a well of n-type material formed in the p-type substrate in direct physical contact with the p-type substrate and electrically connected to the p-type substrate via a first metal line, a well of p-type material formed in the first well of n-type material, a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and connected to the word line of the memory device, and a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and electrically connected to the well of p-type material via a second metal line. The PNP diode includes a n-type substrate connected to ground, a well of p-type material formed in the n-type substrate in direct physical contact with the n-type substrate and electrically connected to the n-type substrate via a first metal line, a well of n-type material formed in the first well of p-type material, a first p-type region formed in the well of n-type material in direct physical contact with the well of n-type material and connected to the word line of the memory device, and a first n-type region formed in the well of p-type material in direct physical contact with the well of p-type material and electrically connected to the well of n-type material via a second metal line.

    摘要翻译： 一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN二极管包括连接到地的p型衬底，在p型衬底中形成的与p型衬底直接物理接触的n型材料的阱，并通过第一金属电连接到p型衬底 线，在n型材料的第一阱中形成的p型材料的阱，形成在p型材料的阱中的第一n型区，与p型材料的阱直接物理接触并连接到 存储器件的字线和形成在n型材料的阱中的与n型材料的阱直接物理接触并且经由第二p型材料电连接到p型材料的阱的第一p型区域 金属线。 PNP二极管包括连接到地的n型衬底，形成在n型衬底中的p型材料的阱与n型衬底直接物理接触并且经由第一金属电连接到n型衬底 线，在p型材料的第一阱中形成的n型材料的阱，形成在n型材料的阱中的与n型材料的阱直接物理接触的第一p型区，并连接到 存储器件的字线和形成在p型材料的阱中的第一n型区域，其与p型材料的阱直接物理接触并且经由第二类型的n型材料电连接到n型材料的阱 金属线。

    Back-to-back NPN/PNP protection diodes
    5.
    发明授权
    Back-to-back NPN/PNP protection diodes 有权
    背对背NPN / PNP保护二极管

    公开(公告)号：US07285827B1

    公开(公告)日：2007-10-23

    申请号：US11194449

    申请日：2005-08-02

    申请人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

    发明人： Yi He ,  Zhizheng Liu ,  Meng Ding ,  Wei Zheng

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0266 ,  H01L27/0255

    摘要： A device includes a memory device and an NPN or PNP diode coupled to a word-line of the memory device. The NPN or PNP diode reduces device damage and performance impairment that may result from device charging by drawing charges away from the memory device.

    摘要翻译： 一种设备包括存储器件和耦合到存储器件的字线的NPN或PNP二极管。 NPN或PNP二极管通过从存储器件中抽取电荷来减少设备充电所造成的器件损坏和性能损害。

    Flash memory cell and methods for programming and erasing
    6.
    发明申请
    Flash memory cell and methods for programming and erasing 有权

    公开(公告)号：US20060291282A1

    公开(公告)日：2006-12-28

    申请号：US11511763

    申请日：2006-08-29

    申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

    发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

    IPC分类号： G11C11/34

    CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

    摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

    Flash memory cell and methods for programming and erasing
    7.
    发明授权
    Flash memory cell and methods for programming and erasing 有权
    闪存单元和编程和擦除的方法

    公开(公告)号：US07120063B1

    公开(公告)日：2006-10-10

    申请号：US10841850

    申请日：2004-05-07

    申请人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

    发明人： Zhizheng Liu ,  Zengtao Liu ,  Yi He ,  Mark Randolph

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L29/66833

    摘要： Flash memory cells are presented which comprise a dielectric material formed above a substrate channel region, a charge trapping material formed over the dielectric material, and a control gate formed over the charge trapping material. The cell may be programmed by directing electrons from the control gate into the charge trapping material to raise the cell threshold voltage. The electrons may be directed from the control gate to the charge trapping material by coupling a substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is lower than the substrate voltage potential. The cell may be erased by directing electrons from the charge trapping material into the control gate to lower a threshold voltage of the flash memory cell, such as by coupling the substrate to a substrate voltage potential, and coupling the control gate to a gate voltage potential, where the gate voltage potential is higher than the substrate voltage potential.

    摘要翻译： 提供了闪存单元，其包括形成在衬底沟道区上方的电介质材料，在电介质材料上形成的电荷俘获材料，以及形成在电荷俘获材料上的控制栅。 可以通过将电子从控制栅极引导到电荷捕获材料中来提高电池阈值电压来编程电池。 电子可以通过将衬底耦合到衬底电压电势，并将控制栅极耦合到栅极电压电位，其中栅极电压电位低于衬底电压电位，从控制栅极引导到电荷俘获材料。 可以通过将电子从电荷捕获材料引入控制栅极来降低闪速存储器单元的阈值电压，例如通过将衬底耦合到衬底电压电位，以及将控制栅极耦合到栅极电压电位来擦除电池 ，其中栅极电压电位高于衬底电压电位。

    System and method for erasing a memory cell
    9.
    发明授权
    System and method for erasing a memory cell 有权
    擦除存储单元的系统和方法

    公开(公告)号：US07167398B1

    公开(公告)日：2007-01-23

    申请号：US11062641

    申请日：2005-02-23

    申请人： Zhizheng Liu ,  Satoshi Torii ,  Mark Randolph ,  Yi He

    发明人： Zhizheng Liu ,  Satoshi Torii ,  Mark Randolph ,  Yi He

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/0475 ,  G11C16/14 ,  H01L29/66833 ,  H01L29/7923

    摘要： A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and erasing the group of storage regions of the first memory cell via a single hot hole injection process.

    摘要翻译： 一种方法擦除包括一组存储单元的半导体器件的存储单元。 每个存储单元包括一组存储区域。 该方法包括：通过单个热孔注入处理确定要擦除第一存储器单元组的存储区域的每个存储区域并擦除第一存储单元的存储区域组。