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公开(公告)号：US08212310B2
公开(公告)日：2012-07-03
申请号：US13022611
申请日：2011-02-07
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L21/266 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.
摘要翻译： 半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。 通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。
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公开(公告)号：US08110924B2
公开(公告)日：2012-02-07
申请号：US12408390
申请日：2009-03-20
CPC分类号： H01L23/585 , H01L23/522 , H01L23/552 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/1132 , H01L2224/1191 , H01L2224/13022 , H01L2224/13025 , H01L2224/13099 , H01L2224/1411 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01051 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit.
摘要翻译： 在DC-DC转换器中，在硅衬底上设置多层布线层，并且在硅衬底和多层布线层中形成控制输入电路和输出电路的控制电路。 此外，设置覆盖多层布线层的密封树脂层和连接到多层布线层的最上布线的连接构件，其穿透密封树脂层并具有从密封树脂层的上表面突出的上端部。 连接构件的上端部由突出电极形成。 与输出电路的端子连接的连接构件的水平横截面面积大于与控制电路的端子连接的连接构件的水平截面积。
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公开(公告)号：US20110298528A1
公开(公告)日：2011-12-08
申请号：US13052269
申请日：2011-03-21
IPC分类号： H03K3/011
CPC分类号： H03K19/00369 , H01L2224/05554 , H01L2224/0603 , H01L2224/48137 , H01L2224/48247 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H03K17/6871 , H03K2017/0806 , H01L2924/00
摘要： According to one embodiment, a power semiconductor system includes; a first power semiconductor element, a driver IC, a first temperature detection element, a control circuit and an overheat protection control section. The first power semiconductor element controls current flowing between a first electrode and a second electrode with a control electrode. The driver IC supplies a drive signal making the first power semiconductor element on and off. The first temperature detection element detects a temperature of the driver IC. The control circuit supplies a control signal for controlling operation of the driver IC to the driver IC. The overheat protection control section is configured to supply an overheat protection signal to the control circuit based on an output of the first temperature detection element. The control circuit performs overheat protection operation. The overheat protection control section supplies the overheat protection signal to the control circuit.
摘要翻译： 根据一个实施例，功率半导体系统包括： 第一功率半导体元件，驱动器IC，第一温度检测元件，控制电路和过热保护控制部。 第一功率半导体元件通过控制电极控制在第一电极和第二电极之间流动的电流。 驱动器IC提供使第一功率半导体元件接通和断开的驱动信号。 第一温度检测元件检测驱动器IC的温度。 控制电路向驱动器IC提供用于控制驱动器IC的操作的控制信号。 过热保护控制部根据第一温度检测元件的输出，将过热保护信号提供给控制电路。 控制电路进行过热保护动作。 过热保护控制部分将过热保护信号提供给控制电路。
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24.发明授权公开(公告)号：US08067928B2
公开(公告)日：2011-11-29
申请号：US12473698
申请日：2009-05-28
申请人： Kazutoshi Nakamura , Toshiyuki Naka
发明人： Kazutoshi Nakamura , Toshiyuki Naka
CPC分类号： H02M3/1588 , H02M2001/0019 , H02M2001/0048 , H03K2217/0081 , Y02B70/1466 , Y02B70/1491
摘要： A DC-DC converter includes a high side transistor and a low side transistor connected in series between an input potential and a grounding potential, and an LC filter connected between a connection point of the both transistors and an output terminal. A control unit controls the gate potential of the high side transistor in an ON state and the gate potential of the low side transistor in an ON state according to a magnitude of a current output from the output terminal.
摘要翻译： DC-DC转换器包括串联连接在输入电位和接地电位之间的高侧晶体管和低侧晶体管，以及连接在两晶体管的连接点和输出端之间的LC滤波器。 控制单元根据从输出端子输出的电流的大小，将处于导通状态的高侧晶体管的栅极电位和低侧晶体管的栅极电位控制在导通状态。
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公开(公告)号：US07906808B2
公开(公告)日：2011-03-15
申请号：US12476147
申请日：2009-06-01
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7835 , H01L21/266 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1087 , H01L29/66659
摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.
摘要翻译： 半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。 通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。
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公开(公告)号：US07893744B2
公开(公告)日：2011-02-22
申请号：US12351426
申请日：2009-01-09
申请人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： H03K3/017
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译： 一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。 第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。
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公开(公告)号：US20090295341A1
公开(公告)日：2009-12-03
申请号：US12473698
申请日：2009-05-28
申请人： Kazutoshi Nakamura , Toshiyuki Naka
发明人： Kazutoshi Nakamura , Toshiyuki Naka
IPC分类号： G05F1/46
CPC分类号： H02M3/1588 , H02M2001/0019 , H02M2001/0048 , H03K2217/0081 , Y02B70/1466 , Y02B70/1491
摘要： A DC-DC converter includes a high side transistor and a low side transistor connected in series between an input potential and a grounding potential, and an LC filter connected between a connection point of the both transistors and an output terminal. A control unit controls the gate potential of the high side transistor in an ON state and the gate potential of the low side transistor in an ON state according to a magnitude of a current output from the output terminal.
摘要翻译： DC-DC转换器包括串联连接在输入电位和接地电位之间的高侧晶体管和低侧晶体管，以及连接在两晶体管的连接点和输出端之间的LC滤波器。 控制单元根据从输出端子输出的电流的大小，将处于导通状态的高侧晶体管的栅极电位和低侧晶体管的栅极电位控制在导通状态。
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公开(公告)号：US20090179681A1
公开(公告)日：2009-07-16
申请号：US12351426
申请日：2009-01-09
申请人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： G06F1/04
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译： 一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。 第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。
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公开(公告)号：US07253473B2
公开(公告)日：2007-08-07
申请号：US11245204
申请日：2005-10-07
申请人： Kazutoshi Nakamura , Syotaro Ono
发明人： Kazutoshi Nakamura , Syotaro Ono
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42372 , H01L29/42376 , H01L29/4933 , H01L29/66719 , H01L29/66734
摘要： A semiconductor device includes: a semiconductor substrate of the first-type; a semiconductor region of the first-type formed on the substrate; a gate electrode a part of which is present within a trench selectively formed in part of the semiconductor region, and an extended top-end to have a wide width via a stepped-portion; a gate insulating-film formed between the trench and the gate electrode along a wall surface of the trench; a base layer of the second-type on the region via the film to enclose a side-wall except a bottom of the trench; a source region of the first-type adjacent to the film outside the trench in the vicinity of a top surface of the base layer; and an insulating-film formed partially between a bottom-surface of the top-end and a top-surface of the source region and formed to have a thickness larger than that of the gate insulating-film within the trench.
摘要翻译： 半导体器件包括：第一类型的半导体衬底; 在基板上形成第一类型的半导体区域; 栅极电极，其一部分存在于在半导体区域的一部分中选择性地形成的沟槽中，并且延伸的顶端经由阶梯部分具有宽的宽度; 栅沟绝缘膜，沿着沟槽的壁表面形成在沟槽和栅电极之间; 经由膜在该区域上的第二类型的基底层以包围沟槽底部以外的侧壁; 所述第一类型的源极区域在所述基底层的顶表面附近与所述沟槽外部的膜相邻; 以及部分地形成在顶部的底表面和源极区的顶表面之间并且形成为具有比沟槽内的栅极绝缘膜的厚度大的厚度的绝缘膜。
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公开(公告)号：US20060097292A1
公开(公告)日：2006-05-11
申请号：US11261531
申请日：2005-10-31
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/1045 , H01L29/42368 , H01L29/7835
摘要： A semiconductor device includes a second conductivity type layer selectively formed by changing impurity concentrations on a semiconductor substrate, a first conductivity type source region formed on the second conductivity type layer, a first conductivity type drain region formed on the second conductivity type layer apart from the first conductivity type source region, a gate electrode formed between the first conductivity type source region and the first conductivity type drain region across an insulation film, and a second conductivity type contact layer formed adjacent to the first conductivity type source region, wherein the second conductivity type layer in the source region side has a higher impurity concentration than the impurity concentration of the second conductivity type layer in the drain region side.
摘要翻译： 半导体器件包括通过改变半导体衬底上的杂质浓度选择性地形成的第二导电类型层，形成在第二导电类型层上的第一导电型源极区，形成在第二导电类型层上的第一导电类型漏极区， 第一导电型源极区，形成在绝缘膜之间的第一导电型源极区域和第一导电型漏极区域之间的栅电极和与第一导电型源极区域相邻形成的第二导电型接触层，其中第二导电型源极区域 源极区侧的杂质浓度比漏区侧的第二导电型层的杂质浓度高。
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