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公开(公告)号：US20080121950A1
公开(公告)日：2008-05-29
申请号：US11771340
申请日：2007-06-29
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66575 , H01L29/7833 , H01L29/7848
摘要： Even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is realized.The channel length direction of n channel MISFET where the silicide region of nickel or a nickel alloy was formed on the source and the drain is arranged so that it may become parallel to the crystal orientation of a semiconductor substrate. Since it is hard to extend the silicide region of nickel or a nickel alloy in the direction of crystal orientation , even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is obtained.
摘要翻译： 即使是在n沟道MISFET的源极和漏极中形成镍或镍合金的硅化物区域的情况，也可以实现OFF泄漏电流容易增加的半导体器件。 在源极和漏极上形成镍或镍合金的硅化物区域的n沟道MISFET的沟道长度方向被布置成使其可以平行于半导体衬底的晶体取向<100>。 由于难以在晶体取向<100>的方向上延伸镍或镍合金的硅化物区域，所以即使在镍或镍合金的硅化物区域形成在n的源极和漏极中的情况 通道MISFET，可以容易地提高OFF漏电流的半导体装置。
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公开(公告)号：US06479856B1
公开(公告)日：2002-11-12
申请号：US09435214
申请日：1999-11-05
申请人： Keiichiro Kashihara
发明人： Keiichiro Kashihara
IPC分类号： H01L27108
CPC分类号： H01L28/55 , H01L27/10814 , H01L28/75
摘要： A Layered product (70) is formed on a high-dielectric-constant layer (64). The layered product has a layered structure consisting of an upper electrode (71), a barrier layer (72), a stopper layer (73) and an adhesion layer (74) in this order from the near side of the high-dielectric-constant layer (64). For the high-dielectric-constant layer (64), the upper electrode (71), the barrier layer (72), the stopper layer (73) and the adhesion layer (74), BST, Pt or PtOa, TiN or TiSiN, PtSixOyNz (0
摘要翻译： 在高介电常数层（64）上形成层状产物（70）。 层叠体的高介电常数的近侧依次具有上部电极（71），阻挡层（72），阻挡层（73）和粘附层（74）的层叠结构 层（64）。 对于高介电常数层（64），上电极（71），阻挡层（72），阻挡层（73）和粘附层（74），BST，Pt或PtOa，TiN或TiSiN， 分别使用PtSixOyNz（0
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23.发明授权Semiconductor device with high dielectric capacitor having sidewall spacers 失效具有高介电电容器的半导体器件具有侧壁间隔物
公开(公告)号：US5442213A
公开(公告)日：1995-08-15
申请号：US255854
申请日：1994-06-07
IPC分类号： H01L21/28 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L23/522 , H01L27/04 , H01L27/105 , G11C11/24
CPC分类号： H01L27/10852 , H01L21/3205 , H01L28/40 , H01L28/55 , Y10S257/915 , Y10S438/978
摘要： According to a semiconductor device and a method of manufacturing thereof, a sidewall spacer is formed at a sidewall of a contact hole, in a recess portion defined by the sidewall of the contact hole and a buried conductive layer, having a film thickness gradually increasing from a top face corner of an interlayer insulation film to the surface of the buried conductive layer. Therefore, a semiconductor device that can achieve favorable breakdown voltage and anti-leak characteristics between a lower electrode layer and an upper electrode layer forming a capacitor of a DRAM.
摘要翻译： 根据半导体器件及其制造方法，在由接触孔的侧壁限定的凹部和埋入导电层的接触孔的侧壁处形成侧壁间隔物，其中膜厚度从 层间绝缘膜的顶面角到掩埋导电层的表面。 因此，可以在形成DRAM的电容器的下电极层和上电极层之间实现良好的击穿电压和防漏电特性的半导体装置。
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公开(公告)号：US08148248B2
公开(公告)日：2012-04-03
申请号：US13053733
申请日：2011-03-22
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。
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公开(公告)号：US20120049201A1
公开(公告)日：2012-03-01
申请号：US13182750
申请日：2011-07-14
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/7848
摘要： In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.
摘要翻译： 在CMIS器件中，为了改善通过使用应变硅技术形成的n沟道电场晶体管的工作特性，而不降低p沟道场效应晶体管的工作特性。 在形成pISIS的nMIS和源极/漏极（p型延伸区域和p型扩散区域）的源极/漏极（n型延伸区域和n型扩散区域）之后， 源极/漏极具有所需的浓度分布和电阻，在n型扩散区域中形成具有所需量的应变的Si：C层，因此Si：C层中的最佳寄生电阻和最佳应变量 在nMIS的源/漏中获得。 此外，通过在等于或短于1毫秒的短时间内形成Si：C层进行热处理，已经形成的p型延伸区域的各个p型杂质的浓度分布的变化和 p型扩散区被抑制。
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公开(公告)号：US20080242035A1
公开(公告)日：2008-10-02
申请号：US12014136
申请日：2008-01-15
IPC分类号： H01L21/336
CPC分类号： H01L29/7846 , H01L21/823807 , H01L21/823814 , H01L21/823835 , H01L29/665 , H01L29/7843
摘要： The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate. A barrier film is a film which makes a semiconductor substrate generate tensile stress, and the metal silicide layer which consists of mono-silicide MSi of metallic element M which forms a metallic film is formed in the first heat treatment.
摘要翻译： 提高了在自对准硅化物工艺中形成金属硅化物层的半导体器件的性能。 通过STI法在半导体衬底中形成元件隔离区域，形成栅极绝缘膜，形成栅电极，n + +型半导体区域和p + 形成用于源极/漏极的半导体区域，在半导体衬底上形成金属膜，并且在金属膜上形成阻挡膜。 并且在形成金属硅化物层之后，通过执行第一次金属硅化物层使金属膜和栅极，n + +型半导体区域和p + +型半导体区域反应 除去热处理，阻挡膜和未反应的金属膜，留下金属硅化物层。 元件隔离区使压缩应力作用在半导体衬底上。 阻挡膜是使半导体基板产生拉伸应力的膜，在第一热处理中形成由形成金属膜的金属元素M的单硅化物MSi构成的金属硅化物层。
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27.发明申请METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE CARRYING OUT ION IMPLANTATION BEFORE SILICIDE PROCESS 有权制造半导体器件的方法在硅化工艺之前进行离子植入公开(公告)号：US20070077736A1
公开(公告)日：2007-04-05
申请号：US11537208
申请日：2006-09-29
IPC分类号： H01L21/04
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.
摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。
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公开(公告)号：US06078072A
公开(公告)日：2000-06-20
申请号：US73834
申请日：1998-05-06
IPC分类号： H01L21/02 , H01L21/8242 , H01L29/76 , H01L27/108 , H01L29/94 , H01L31/113
CPC分类号： H01L27/10852 , H01L28/60 , H01L28/55
摘要： A lower electrode layer 1 of a capacitor 10 is formed by sputtering performed at a temperature lower than 450.degree. C. in an atmosphere containing oxygen, and thereby the lower electrode layer 1 thus formed contains oxygen. Thereby, a method of manufacturing a semiconductor device having the capacitor can suppress current leak, and can prevent peeling of an electrode.
摘要翻译： 电容器10的下电极层1通过在低于450℃的温度下在含氧气氛中进行溅射而形成，由此形成的下电极层1含有氧。 因此，制造具有电容器的半导体器件的方法可以抑制电流泄漏，并且可以防止电极的剥离。
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公开(公告)号：US20110207317A1
公开(公告)日：2011-08-25
申请号：US13053733
申请日：2011-03-22
IPC分类号： H01L21/768
CPC分类号： H01L23/485 , H01L21/28518 , H01L2924/0002 , H01L2924/00
摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.
摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。
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30.发明授权Method of manufacturing semiconductor device carrying out ion implantation before silicide process 有权在硅化物处理之前进行离子注入的半导体器件的制造方法公开(公告)号：US07872314B2
公开(公告)日：2011-01-18
申请号：US12727334
申请日：2010-03-19
IPC分类号： H01L23/62
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/823835 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.
摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。
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