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21.发明授权Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor device 有权半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及半导体装置的图案生成装置公开(公告)号：US07171645B2
公开(公告)日：2007-01-30
申请号：US10634988
申请日：2003-08-06
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： To provide a pattern generating method for a semiconductor device capable of forming a highly reliable semiconductor device, the accuracy of which is high.A method of generating a pattern for a semiconductor device comprises: a step of designing and arranging a layout pattern of a semiconductor chip; a step of extracting an area ratio of the mask pattern from the layout pattern; and a step of adding and arranging a dummy pattern to the layout pattern, while consideration is given to the most appropriate area ratio of the layout pattern of the layer obtained according to a process condition of the layer composing the layout pattern, so that the area ratio of the layer can be the most appropriate area ratio.
摘要翻译： 为了提供能够形成高可靠性的半导体器件的半导体器件的图案生成方法，其精度高。 一种生成用于半导体器件的图案的方法包括：设计和布置半导体芯片的布局图案的步骤; 从布局图案提取掩模图案的面积比的步骤; 以及向布局图案添加和布置虚拟图案的步骤，同时考虑根据构成布局图案的层的处理条件获得的层的布局图案的最合适面积比，使得区域 该层的比例可以是最合适的面积比。
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22.发明授权Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor device 失效半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及用于半导体装置的图案的制造装置公开(公告)号：US07062732B2
公开(公告)日：2006-06-13
申请号：US10634989
申请日：2003-08-06
IPC分类号： G06F9/45
CPC分类号： H01L23/585 , G06F17/5068 , H01L27/0203 , H01L2924/0002 , Y02T10/82 , H01L2924/00
摘要： To provide a semiconductor device characterized in that: a decoupling capacitor can be increased; noise generated from an electric power supply can be effectively absorbed; and a stable operation of a circuit can be realized.Irrespective of whether or not a region is close to a power supply wiring or a ground wiring, MOS is spread all over a spare area of a chip and connected to a power supply wiring and ground wiring by utilizing a wiring layer and diffusion layer.
摘要翻译： 提供一种半导体器件，其特征在于：可以增加去耦电容器; 可以有效地吸收从电源产生的噪声; 并且可以实现电路的稳定操作。 无论区域是否接近电源布线或接地布线，MOS都通过利用布线层和扩散层而遍布芯片的备用区域并与电源布线和接地布线相连。
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公开(公告)号：US06943129B2
公开(公告)日：2005-09-13
申请号：US10703605
申请日：2003-11-10
IPC分类号： G06F17/50 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/04
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： A wiring pattern has been enlarged by mutually different values, thereby forming two enlarged wiring patterns are formed. Then, regions where the two enlarged wiring patterns overlap each other are removed, thereby forming a dummy pattern. Alternatively, a simple-figure pattern made of simple figures is formed and a dummy pattern is formed using the simple-figure pattern. A gap that is not wider than a predetermined value is located in a final wiring pattern made of the wiring pattern and the dummy pattern is defined as an air gap region. Thus, an interconnection structure incorporating air gaps between wiring patterns is formed.
摘要翻译： 通过相互不同的值扩大布线图案，从而形成两个放大的布线图案。 然后，去除两个放大布线图案彼此重叠的区域，从而形成虚拟图案。 或者，形成由简单图形构成的简图，并使用简单图案形成虚拟图案。 不大于预定值的间隙位于由布线图案制成的最终布线图形中，并且虚设图案被定义为气隙区域。 因此，形成了在布线图案之间并入气隙的互连结构。
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24.发明授权Mask pattern correction process, photomask and semiconductor integrated circuit device 失效掩模图案校正工艺，光掩模和半导体集成电路器件公开(公告)号：US06303251B1
公开(公告)日：2001-10-16
申请号：US09360989
申请日：1999-07-27
IPC分类号： G03F900
CPC分类号： G03F7/70441 , G03F1/36
摘要： In order that CAD processing time required for modifying an input design pattern to compensate for optical proximity effects is reduced, increases in the number of base shapes when corrected data are converted into EB data are restricted, and false detection of defects in a photomask inspection process is restricted, the following steps are taken. At a shape selection step, rectangular shapes are divided into a dense rectangular shape group and a non-dense rectangular shape group according to the distance of each rectangular shape to an adjacent rectangular shape. At a number-of-shapeas comparison step, the number of shapes included in the dense rectangular shape group is compared to the number of shapes included in the non-dense rectangular shape group to select either shape group for correction. At a correction process selection step, a correction process suited for the selected shape group is selected. At a shape correction step, optical proximity correction is made. At a shape combining step, a group of corrected shapes and the rectangular shape group different from the selected one are combined.
摘要翻译： 为了减少修改输入设计图案以补偿光学邻近效应所需的CAD处理时间，校正数据被转换为EB数据时的基本形状数量的增加受到限制，并且光掩模检查过程中的缺陷的错误检测 被限制，采取以下步骤。 在形状选择步骤中，矩形形状根据每个矩形形状与相邻矩形形状的距离被分成致密矩形形状组和非密集矩形形状组。 在数字形状比较步骤中，将包含在密集矩形形状组中的形状的数量与包括在非致密矩形形状组中的形状的数量进行比较，以选择用于校正的形状组。 在校正处理选择步骤中，选择适合所选择的形状组的校正处理。 在形状校正步骤中，进行光学邻近校正。 在形状组合步骤中，组合一组校正形状和与所选择的形状组不同的矩形形状组合。
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25.发明授权Mask pattern inspecting method, inspection apparatus, inspecting data used therein and inspecting data generating method 有权掩模图案检查方法，检查装置，检查数据，检查数据生成方法公开(公告)号：US07114144B2
公开(公告)日：2006-09-26
申请号：US10722346
申请日：2003-11-26
IPC分类号： G06F17/50
CPC分类号： G03F1/84 , G03F7/70616 , G06T7/0004 , G06T2207/30148
摘要： A method of inspecting a photomask for a semiconductor integrated circuit formed based on drawing pattern data, includes the steps of classifying a drawing pattern of the semiconductor integrated circuit into a plurality of ranks in accordance with a predetermined reference and extracting the same, determining inspecting accuracy for each of the ranks, and deciding quality of the photomask depending on whether the determined inspecting accuracy is satisfied.
摘要翻译： 一种检查基于绘制图形数据形成的半导体集成电路的光掩模的方法，包括以下步骤：根据预定的参考将半导体集成电路的绘制图案分类成多个等级并提取它们，并提取它们，确定检查精度 并且根据所确定的检查精度是否满足来确定光掩模的质量。
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26.发明授权Latch-up verifying method and latch-up verifying apparatus capable of varying over-sized region 失效能够改变超大尺寸区域的锁存验证方法和闩锁验证装置公开(公告)号：US06718528B2
公开(公告)日：2004-04-06
申请号：US10303470
申请日：2002-11-25
IPC分类号： G06F1750
CPC分类号： G06F17/5081 , G06F17/5036
摘要： With respect to layout data of a semiconductor integrated circuit, a latch-up verifying operation is carried out in high precision. In a latch-up verifying method, a well region, a transistor region, and a substrate contact region are extracted from layout data of a semiconductor integrated circuit formed on a semiconductor substrate; and steps for separately setting over-sizing values are sequentially executed based upon the respective extracted information.
摘要翻译： 对于半导体集成电路的布局数据，以高精度执行闩锁验证操作。 在闩锁验证方法中，从形成在半导体衬底上的半导体集成电路的布局数据中提取阱区域，晶体管区域和衬底接触区域; 并且基于相应提取的信息顺序地执行用于单独设置过大尺寸值的步骤。
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公开(公告)号：US06434730B1
公开(公告)日：2002-08-13
申请号：US09484022
申请日：2000-01-18
IPC分类号： G06F1750
CPC分类号： H01L23/5223 , G06F17/5068 , H01L23/5286 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： After a layout for a semiconductor device including power and ground lines has been defined, patterns for bypass capacitors, which will be located under the power lines, are created. In this case, a pattern for a semiconductor device, where a bypass capacitor array is inlaid and substrate contacts are located under ground lines, is defined based on design rules input. Next, power lines are extracted and resized. Thereafter, logical operations are performed to place the bypass capacitors and the bypass capacitors are resized. Subsequently, logical operations are performed to define interconnecting diffused layers and the diffused layers are resized. Since the patterns for the power lines have already been defined before the patterns for the bypass capacitors are created, the patterns for the bypass capacitors to be placed under the power lines can be defined automatically. Thus, a pattern for a miniaturized semiconductor device with reduced power supply noise can be created automatically.
摘要翻译： 在定义了包括电源和接地线的半导体器件的布局之后，创建将位于电力线下方的用于旁路电容器的图案。 在这种情况下，基于设计规则输入来定义用于嵌入旁路电容器阵列并且衬底接触的半导体器件的图案位于地线下方。 接下来，提取电源线并调整大小。 此后，进行逻辑运算以放置旁路电容器和旁路电容器大小。 随后，执行逻辑操作以定义互连扩散层，并且扩散层被调整大小。 由于在创建旁路电容器的图案之前已经定义了电源线的图案，因此可以自动定义用于放置在电力线下方的旁路电容器的图案。 因此，可以自动地产生具有降低的电源噪声的小型化半导体器件的图案。
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28.发明授权Semiconductor device geometrical pattern correction process and geometrical pattern extraction process 失效半导体器件几何图案校正过程和几何图案提取过程公开(公告)号：US06183920B2
公开(公告)日：2001-02-06
申请号：US09348316
申请日：1999-07-07
IPC分类号： G03F900
CPC分类号： G03F7/70441 , G03F1/36
摘要： A semiconductor device geometrical pattern correction process, semiconductor device manufacturing process and geometrical pattern extraction process are provided, which make it possible to eliminate the adverse effect of corner rounding accompanying miniaturization, that is, a decrease in the projection amount of a gate, while avoiding increased chip area. The correction process comprises a step 102 of detecting a concave diffusion layer corresponding portion and a step 103 of correcting either the concave diffusion layer corresponding portion or a transistor gate corresponding portion which projects from the concave diffusion layer corresponding portion in order to ensure the projection of the gate from the concave diffusion layer corresponding portion against possible corner rounding.
摘要翻译： 提供半导体器件几何图案校正处理，半导体器件制造工艺和几何图案提取处理，这可以消除伴随着小型化的圆角倒圆的不良影响，即，避免浇口的投影量的减少，同时避免 增加芯片面积。 校正处理包括检测凹面扩散层对应部分的步骤102和校正从凹形扩散层对应部分突出的凹形扩散层对应部分或晶体管栅极对应部分的步骤103，以确保投影 来自凹面扩散层的对应部分的栅极可能围绕可能的角落四舍五入。
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