公开(公告)号：US07171645B2

公开(公告)日：2007-01-30

申请号：US10634988

申请日：2003-08-06

申请人： Mitsumi Ito ,  Junichi Shimada ,  Kiyohito Mukai ,  Hiroyuki Tsujikawa

发明人： Mitsumi Ito ,  Junichi Shimada ,  Kiyohito Mukai ,  Hiroyuki Tsujikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

摘要： To provide a pattern generating method for a semiconductor device capable of forming a highly reliable semiconductor device, the accuracy of which is high.A method of generating a pattern for a semiconductor device comprises: a step of designing and arranging a layout pattern of a semiconductor chip; a step of extracting an area ratio of the mask pattern from the layout pattern; and a step of adding and arranging a dummy pattern to the layout pattern, while consideration is given to the most appropriate area ratio of the layout pattern of the layer obtained according to a process condition of the layer composing the layout pattern, so that the area ratio of the layer can be the most appropriate area ratio.

摘要翻译： 为了提供能够形成高可靠性的半导体器件的半导体器件的图案生成方法，其精度高。 一种生成用于半导体器件的图案的方法包括：设计和布置半导体芯片的布局图案的步骤; 从布局图案提取掩模图案的面积比的步骤; 以及向布局图案添加和布置虚拟图案的步骤，同时考虑根据构成布局图案的层的处理条件获得的层的布局图案的最合适面积比，使得区域 该层的比例可以是最合适的面积比。

公开(公告)号：US07062732B2

公开(公告)日：2006-06-13

申请号：US10634989

申请日：2003-08-06

申请人： Mitsumi Ito ,  Junichi Shimada ,  Kiyohito Mukai ,  Hiroyuki Tsujikawa

发明人： Mitsumi Ito ,  Junichi Shimada ,  Kiyohito Mukai ,  Hiroyuki Tsujikawa

IPC分类号： G06F9/45

CPC分类号： H01L23/585 ,  G06F17/5068 ,  H01L27/0203 ,  H01L2924/0002 ,  Y02T10/82 ,  H01L2924/00

摘要： To provide a semiconductor device characterized in that: a decoupling capacitor can be increased; noise generated from an electric power supply can be effectively absorbed; and a stable operation of a circuit can be realized.Irrespective of whether or not a region is close to a power supply wiring or a ground wiring, MOS is spread all over a spare area of a chip and connected to a power supply wiring and ground wiring by utilizing a wiring layer and diffusion layer.

摘要翻译： 提供一种半导体器件，其特征在于：可以增加去耦电容器; 可以有效地吸收从电源产生的噪声; 并且可以实现电路的稳定操作。 无论区域是否接近电源布线或接地布线，MOS都通过利用布线层和扩散层而遍布芯片的备用区域并与电源布线和接地布线相连。

公开(公告)号：US20050172248A1

公开(公告)日：2005-08-04

申请号：US10886704

申请日：2004-07-09

申请人： Junichi Shimada ,  Fumihiro Kimura ,  Mitsumi Ito ,  Kiyohito Mukai

发明人： Junichi Shimada ,  Fumihiro Kimura ,  Mitsumi Ito ,  Kiyohito Mukai

IPC分类号： G06F17/50 ,  G06F9/45 ,  H01L21/3205 ,  H01L21/82 ,  H01L23/52

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed on an assumption that a dummy pattern defined by process conditions is placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region in at least one instance provided in the semiconductor integrated circuit device.

摘要翻译： 假设半导体集成电路器件的模式面积比的验证或半导体集成电路器件设置的检查窗口中的图案占有率是在将半导体集成电路器件的未占用区域放置在由半导体集成电路器件的未占用区域 集成电路器件或在半导体集成电路器件中设置的至少一个实例中的未占用区域中。

公开(公告)号：US07269807B2

公开(公告)日：2007-09-11

申请号：US10886704

申请日：2004-07-09

申请人： Junichi Shimada ,  Fumihiro Kimura ,  Mitsumi Ito ,  Kiyohito Mukai

发明人： Junichi Shimada ,  Fumihiro Kimura ,  Mitsumi Ito ,  Kiyohito Mukai

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

摘要： Verification of the pattern area ratio of a semiconductor integrated circuit device or the pattern occupancy ratio in a check window set for the semiconductor integrated circuit device is performed on an assumption that a dummy pattern defined by process conditions is placed in an unoccupied region of the semiconductor integrated circuit device or in an unoccupied region in at least one instance provided in the semiconductor integrated circuit device.

摘要翻译： 在半导体集成电路器件设定的检查窗口中，对半导体集成电路器件的图案面积比率或图案占有率的验证是在将由工艺条件限定的虚设图案置于半导体集成电路的未占用区域中的假设下进行的 集成电路器件或在半导体集成电路器件中提供的至少一个实例中的未占用区域中。

公开(公告)号：US20070020880A1

公开(公告)日：2007-01-25

申请号：US11522995

申请日：2006-09-19

申请人： Kiyohito Mukai ,  Tadashi Tanimoto ,  Mitsumi Ito

发明人： Kiyohito Mukai ,  Tadashi Tanimoto ,  Mitsumi Ito

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  G06F17/5068 ,  H01L21/76229

摘要： At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.

摘要翻译： 至少形成用于将半导体衬底分离成相对大面积的第一区域和相对较小面积的第二区域的沟槽。 在包括凹槽内部的半导体衬底的表面上形成绝缘膜。 使用具有格子窗图案的蚀刻掩模蚀刻绝缘膜，使得在第一区域中形成与格子窗图案对应的开口。 作为替代，使用具有单一开口图案和格子窗口图案的蚀刻掩模，在第一区域中形成对应于单个开口图案的开口，并且以与栅格窗口图案相对应的开口蚀刻绝缘膜 形成在第二区域中。 在这两种情况下，剩余的绝缘膜被抛光。

公开(公告)号：US07707523B2

公开(公告)日：2010-04-27

申请号：US11522995

申请日：2006-09-19

申请人： Kiyohito Mukai ,  Tadashi Tanimoto ,  Mitsumi Ito

发明人： Kiyohito Mukai ,  Tadashi Tanimoto ,  Mitsumi Ito

IPC分类号： G06F17/50

CPC分类号： H01L21/31053 ,  G06F17/5068 ,  H01L21/76229

摘要： At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.

摘要翻译： 至少形成用于将半导体衬底分离成相对大面积的第一区域和相对较小面积的第二区域的沟槽。 在包括凹槽内部的半导体衬底的表面上形成绝缘膜。 使用具有格子窗图案的蚀刻掩模蚀刻绝缘膜，使得在第一区域中形成与格子窗图案对应的开口。 作为替代，使用具有单一开口图案和格子窗口图案的蚀刻掩模，在第一区域中形成对应于单个开口图案的开口，并且以与栅格窗口图案相对应的开口蚀刻绝缘膜 形成在第二区域中。 在这两种情况下，剩余的绝缘膜被抛光。

公开(公告)号：US07115478B2

公开(公告)日：2006-10-03

申请号：US10663642

申请日：2003-09-17

申请人： Kiyohito Mukai ,  Tadashi Tanimoto ,  Mitsumi Ito

发明人： Kiyohito Mukai ,  Tadashi Tanimoto ,  Mitsumi Ito

IPC分类号： H01L21/76

CPC分类号： H01L21/31053 ,  G06F17/5068 ,  H01L21/76229

摘要： At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.

摘要翻译： 至少形成用于将半导体衬底分离成相对大面积的第一区域和相对较小面积的第二区域的沟槽。 在包括凹槽内部的半导体衬底的表面上形成绝缘膜。 使用具有格子窗图案的蚀刻掩模蚀刻绝缘膜，使得在第一区域中形成与格子窗图案对应的开口。 作为替代，使用具有单一开口图案和格子窗口图案的蚀刻掩模，在第一区域中形成对应于单个开口图案的开口，并且以与栅格窗口图案相对应的开口蚀刻绝缘膜 形成在第二区域中。 在这两种情况下，剩余的绝缘膜被抛光。

公开(公告)号：US06434730B1

公开(公告)日：2002-08-13

申请号：US09484022

申请日：2000-01-18

申请人： Mitsumi Ito ,  Hiroyuki Tsujikawa ,  Seijiro Kojima ,  Masatoshi Sawada

发明人： Mitsumi Ito ,  Hiroyuki Tsujikawa ,  Seijiro Kojima ,  Masatoshi Sawada

IPC分类号： G06F1750

CPC分类号： H01L23/5223 ,  G06F17/5068 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： After a layout for a semiconductor device including power and ground lines has been defined, patterns for bypass capacitors, which will be located under the power lines, are created. In this case, a pattern for a semiconductor device, where a bypass capacitor array is inlaid and substrate contacts are located under ground lines, is defined based on design rules input. Next, power lines are extracted and resized. Thereafter, logical operations are performed to place the bypass capacitors and the bypass capacitors are resized. Subsequently, logical operations are performed to define interconnecting diffused layers and the diffused layers are resized. Since the patterns for the power lines have already been defined before the patterns for the bypass capacitors are created, the patterns for the bypass capacitors to be placed under the power lines can be defined automatically. Thus, a pattern for a miniaturized semiconductor device with reduced power supply noise can be created automatically.

摘要翻译： 在定义了包括电源和接地线的半导体器件的布局之后，创建将位于电力线下方的用于旁路电容器的图案。 在这种情况下，基于设计规则输入来定义用于嵌入旁路电容器阵列并且衬底接触的半导体器件的图案位于地线下方。 接下来，提取电源线并调整大小。 此后，进行逻辑运算以放置旁路电容器和旁路电容器大小。 随后，执行逻辑操作以定义互连扩散层，并且扩散层被调整大小。 由于在创建旁路电容器的图案之前已经定义了电源线的图案，因此可以自动定义用于放置在电力线下方的旁路电容器的图案。 因此，可以自动地产生具有降低的电源噪声的小型化半导体器件的图案。

公开(公告)号：US07831949B2

公开(公告)日：2010-11-09

申请号：US11819573

申请日：2007-06-28

申请人： Shinya Tokunaga ,  Mitsumi Ito ,  Nobufusa Iwanishi ,  Koichi Seko ,  Hiroaki Suzuki ,  Hiroyuki Tanaka ,  Yuichi Nishimura ,  Kazuhiko Fujimoto

发明人： Shinya Tokunaga ,  Mitsumi Ito ,  Nobufusa Iwanishi ,  Koichi Seko ,  Hiroaki Suzuki ,  Hiroyuki Tanaka ,  Yuichi Nishimura ,  Kazuhiko Fujimoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.

摘要翻译： 为了提供一种设计具有高可加工性的半导体集成电路的方法，同时也增加了LSI的规模，并提高了集成度，并设计了一种半导体集成电路系统，其中不必要的辐射被减少，并且在 热特性，实现了与传统技术相反的设计流程，并且首先设计诸如印刷电路板的安装基板，并且基于安装的设计结果设计用于安装LSI的封装基板 然后执行基板和要安装在封装基板上的LSI的布局设计。

公开(公告)号：US20110012260A1

公开(公告)日：2011-01-20

申请号：US12892273

申请日：2010-09-28

申请人： Shinya TOKUNAGA ,  Mitsumi Ito ,  Nobufusa Iwanishi ,  Koichi Seko ,  Hiroaki Suzuki ,  Hiroyuki Tanaka ,  Yuichi Nishimura ,  Kazuhiko Fujimoto

发明人： Shinya TOKUNAGA ,  Mitsumi Ito ,  Nobufusa Iwanishi ,  Koichi Seko ,  Hiroaki Suzuki ,  Hiroyuki Tanaka ,  Yuichi Nishimura ,  Kazuhiko Fujimoto

IPC分类号： H01L23/485 ,  G06F17/50

CPC分类号： G06F17/5068 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/49112 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.

摘要翻译： 为了提供一种设计具有高可加工性的半导体集成电路的方法，同时也增加了LSI的规模，并提高了集成度，并设计了一种半导体集成电路系统，其中不必要的辐射被减少，并且在 热特性，实现了与传统技术相反的设计流程，并且首先设计诸如印刷电路板的安装基板，并且基于安装的设计结果设计用于安装LSI的封装基板 然后执行基板和要安装在封装基板上的LSI的布局设计。