公开(公告)号：US06581173B2

公开(公告)日：2003-06-17

申请号：US09844927

申请日：2001-04-26

申请人： David I. Poisner

发明人： David I. Poisner

IPC分类号： G11C2900

CPC分类号： G06F11/1497 ,  G06F11/1004 ,  G06F11/14

摘要： An integrated circuit device includes dedicated memory verification logic to compare data read from a set of cells in a memory at a first time to data read from the same set of memory cells at a second time.

摘要翻译： 集成电路装置包括专用存储器验证逻辑，用于将从第一时间存储器中的一组单元读取的数据与第二次从同一组存储器单元读取的数据进行比较。

公开(公告)号：US06564330B1

公开(公告)日：2003-05-13

申请号：US09472096

申请日：1999-12-23

申请人： Alberto J. Martinez ,  David I. Poisner ,  Karthi R. Vadivelu

发明人： Alberto J. Martinez ,  David I. Poisner ,  Karthi R. Vadivelu

IPC分类号： G06F126

CPC分类号： G06F1/24

摘要： A wake up circuit for a computer system with a codec controller. The circuit provides a wakeup signal to the computer system when a codec detects an event that requires the system to become active. This signal is provided whether the communications link between the codecs and their controller is active or inactive. When the link is inactive, as indicated by the absence of a bit clock, a data signal on any of the codec input lines triggers the controller to send a power activation signal to the system and to initiate an activation of the codec link. If the link is already active, the general purpose input status change bit is transmitted to the controller, which writes it into a register that is used to trigger a power activation signal to the system. An enable input permits the wakeup signal to be enabled or disabled under program control. The wakeup signal can be used to trigger a system management interrupt or other interrupt suitable for initiating a system resume function.

摘要翻译： 用于具有编解码器控制器的计算机系统的唤醒电路。 当编解码器检测到需要系统激活的事件时，该电路向计算机系统提供唤醒信号。 提供该信号是否编解码器与其控制器之间的通信链路是活动的还是非活动的。 当链路处于非活动状态时，如没有位时钟所示，任何编解码器输入线上的数据信号触发控制器向系统发送电源激活信号并启动编解码器链路的激活。 如果链路已经处于活动状态，则通用输入状态改变位被发送到控制器，控制器将其写入用于触发系统功率激活信号的寄存器。 启用输入允许在程序控制下启用或禁用唤醒信号。 唤醒信号可用于触发适用于启动系统恢复功能的系统管理中断或其他中断。

公开(公告)号：US06421765B1

公开(公告)日：2002-07-16

申请号：US09340498

申请日：1999-06-30

申请人： David I. Poisner

发明人： David I. Poisner

IPC分类号： G06F1300

CPC分类号： G06F12/06

摘要： The present invention is an apparatus and method for selecting one of a first and a second storage element in response to a control signal issued by a processor in a low pin count device. The apparatus comprises a decoder to receive the control signal and an address signal having a select bit indicative of one of the first and the second storage elements. The decoder generates a select signal to access one of the first and the second storage elements based on the select bit.

摘要翻译： 本发明是一种用于响应由处理器在低引脚数设备中发出的控制信号来选择第一和第二存储元件之一的装置和方法。 该装置包括一个解码器，用于接收控制信号和一个具有指示第一和第二存储元件之一的选择位的地址信号。 解码器基于选择位产生选择信号以访问第一和第二存储元件之一。

公开(公告)号：US6131127A

公开(公告)日：2000-10-10

申请号：US936303

申请日：1997-09-24

申请人： Andrew H. Gafken ,  Joseph A. Bennett ,  David I. Poisner

发明人： Andrew H. Gafken ,  Joseph A. Bennett ,  David I. Poisner

IPC分类号： G06F11/00 ,  G06F13/42

CPC分类号： G06F13/423

摘要： A system having a bus coupled to a host and a peripheral controller device each coupled to a bus. The bus includes a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device communicates with the host over the bus to control devices such as parallel port controllers, serial port controllers, super I/O controllers, floppy disk controllers, keyboard controllers and memory devices.

摘要翻译： 具有耦合到主机的总线和每个耦合到总线的外围控制器设备的系统。 总线包括多个通用信号线，用于承载时分复用的地址，数据和控制信息。 外围控制器设备通过总线与主机进行通信，以控制诸如并行端口控制器，串行端口控制器，超级I / O控制器，软盘控制器，键盘控制器和存储器设备之类的设备。

公开(公告)号：US5890012A

公开(公告)日：1999-03-30

申请号：US428572

申请日：1995-04-25

申请人： David I. Poisner

发明人： David I. Poisner

IPC分类号： G06F13/28 ,  G06F13/14 ,  G06F15/16

CPC分类号： G06F13/28

摘要： A slave DMA peripheral achieves the functionalities of a bus master without incurring the costs of additional address and control lines. Information regarding buffers to be accessed is loaded in the peripheral from the CPU. Actual buffer addresses, length values, and direction information are later programmed into the DMA controller by the peripheral. The present invention manages communication between the peripheral and main memory through the DMA controller. This allows the peripheral to access buffers in memory using a minimal number of lines.

摘要翻译： 辅助DMA外设实现总线主机的功能，而不会产生附加地址和控制线的成本。 有关要访问的缓冲区的信息从CPU加载到外设中。 实际缓冲区地址，长度值和方向信息随后由外设编程到DMA控制器中。 本发明通过DMA控制器管理外围和主存储器之间的通信。 这允许外设使用最少数量的行访问存储器中的缓冲区。

公开(公告)号：US20120272090A1

公开(公告)日：2012-10-25

申请号：US13091912

申请日：2011-04-21

申请人： David I. Poisner

发明人： David I. Poisner

IPC分类号： G06F11/08

CPC分类号： G06F11/1415 ,  G06F11/3006 ,  G06F11/3055

摘要： A method for computer system recovery is presented. In one embodiment, the method includes establishing a connection, via an interface, to a computer system to support the system recovery of the computer system. The method includes executing an emulation application as a recovery agent. The method includes retrieving, based on identifiers associated with the computer system, remote data via another interface. The method further includes performing the system recovery by using at least a part of the remote data.

摘要翻译： 介绍了一种计算机系统恢复方法。 在一个实施例中，该方法包括经由接口建立到计算机系统的连接以支持计算机系统的系统恢复。 该方法包括执行仿真应用程序作为恢复代理。 该方法包括基于与计算机系统相关联的标识符，经由另一接口检索远程数据。 该方法还包括通过使用远程数据的至少一部分来执行系统恢复。

公开(公告)号：US07400554B2

公开(公告)日：2008-07-15

申请号：US10037184

申请日：2002-01-02

申请人： David I. Poisner

发明人： David I. Poisner

IPC分类号： G04F10/08

CPC分类号： G06F9/4843 ,  G06F9/4893 ,  Y02D10/24

摘要： A method and apparatus is described for computing a duration of a reduced power consumption state. A time of exiting from the reduced power consumption state is read prior to an execution of an interrupt routine. The read time of exiting is then stored in a register and a calculation of a reduced power consumption state duration may be performed.

摘要翻译： 描述了用于计算降低功耗状态的持续时间的方法和装置。 在执行中断程序之前，读取从降低功耗状态退出的时间。 然后将读出的时间存储在寄存器中，并且可以执行降低的功耗状态持续时间的计算。

公开(公告)号：US07149909B2

公开(公告)日：2006-12-12

申请号：US10143406

申请日：2002-05-09

申请人： Ying Cui ,  Eric C. Samson ,  Ariel Berkovits ,  Aditya Navale ,  David A. Wyatt ,  Leslie E. Cline ,  Joseph W. Tsang ,  Mark A. Blake ,  David I. Poisner ,  William A. Stevens ,  Vijay R. Sar-Dessai

发明人： Ying Cui ,  Eric C. Samson ,  Ariel Berkovits ,  Aditya Navale ,  David A. Wyatt ,  Leslie E. Cline ,  Joseph W. Tsang ,  Mark A. Blake ,  David I. Poisner ,  William A. Stevens ,  Vijay R. Sar-Dessai

IPC分类号： G06F1/32

CPC分类号： G06F1/3228 ,  G06F1/3215 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

公开(公告)号：US07076669B2

公开(公告)日：2006-07-11

申请号：US10122544

申请日：2002-04-15

申请人： David I. Poisner ,  David W. Grawrock ,  James A. Sutton

发明人： David I. Poisner ,  David W. Grawrock ,  James A. Sutton

IPC分类号： H04L9/00

CPC分类号： G06F21/78 ,  G06F21/85

摘要： A method and apparatus to communicate with a token using a previously reserved binary number in the start field of a cycle, wherein the cycle is not echoed on any bus other than the bus through which the communication is received.

公开(公告)号：US07076578B2

公开(公告)日：2006-07-11

申请号：US09186056

申请日：2003-12-22

申请人： David I. Poisner ,  Karthi R. Vadivelu

发明人： David I. Poisner ,  Karthi R. Vadivelu

IPC分类号： G06F13/00

CPC分类号： G06F13/28

摘要： A method and apparatus for a race free data transfer algorithm using hardware based polling. One disclosed method transfers information between a target device and a buffer which is one of a set of buffers. The buffer is pointed to by a current buffer value stored in a controller. The current buffer value is adjusted to point to a next buffer if the current buffer value is different than a last buffer value. One of the set of buffers is serviced utilizing either the current buffer value or the last buffer value from the controller.