公开(公告)号：US20120314211A1

公开(公告)日：2012-12-13

申请号：US13520460

申请日：2010-12-08

申请人： Kimiaki Ando ,  Hiroshi Kikuchi ,  Yuji Inoue

发明人： Kimiaki Ando ,  Hiroshi Kikuchi ,  Yuji Inoue

IPC分类号： G01N21/88

CPC分类号： G01N21/9501 ,  G01N21/47 ,  G01N21/94 ,  H01L22/12

摘要： Provided is a method wherein a multi-anode detector is used for the purpose of detecting scattered light from a wafer, data obtained from the detector (multi-anode) for detecting defects is used, the shape of a beam radiated to the wafer, a rotational shift between the radius direction and the beam long side, and the like are calculated, and the optical axis of the irradiation beam is adjusted. Furthermore, the method is provided with a technique which feeds back the correction quantities for rotation and amplitude to inspection signal data, on the basis of the correction data, and corrects inspection data. Since fine correction with the adjustment of an optics system and signal processing is made possible, positional accuracy of defect inspection and accuracy of defect level (defect size) are improved.

摘要翻译： 提供了一种多阳极检测器用于检测来自晶片的散射光的方法，使用从用于检测缺陷的检测器（多阳极）获得的数据，辐射到晶片的光束的形状， 计算半径方向与光束长边之间的旋转偏移等，并调整照射光束的光轴。 此外，该方法具有基于校正数据将检查信号数据的旋转和振幅校正量反馈并校正检查数据的技术。 由于通过光学系统的调整和信号处理的精细校正成为可能，故缺陷检查的位置精度和缺陷水平（缺陷尺寸）的精度提高。

公开(公告)号：US07643462B2

公开(公告)日：2010-01-05

申请号：US10559685

申请日：2004-05-27

申请人： Kimiaki Ando

发明人： Kimiaki Ando

IPC分类号： H04B7/216 ,  H04B7/00

CPC分类号： H04B1/712

摘要： A receiver allows a user to select received data before de-spreading or symbol data after de-spreading according to various factors when data is simultaneously received via multiple channels and to store the selected data, reduces the capacity of the storage memory, and enhances the degree of freedom of the timing of de-spreading processing. Storing the received data in the storage memory not in the form of symbol data produced after de-spreading but in the form of received data before de-spreading. This reduces the capacity of the storage memory and enhances the degree of the freedom of the timing of the de-spreading process.

摘要翻译： 接收机允许用户在通过多个信道同时接收数据并且存储所选择的数据时，根据各种因素在解扩后选择接收数据或解扩后的符号数据，降低存储存储器的容量，并且增强 解扩处理时间的自由度。 将接收的数据存储在存储存储器中，不是以解扩展之后产生的符号数据的形式，而是在解扩之前以接收数据的形式存储。 这降低了存储存储器的容量并增加了解扩过程的定时自由度。

公开(公告)号：US07313173B2

公开(公告)日：2007-12-25

申请号：US10312583

申请日：2002-04-04

申请人： Kimiaki Ando

发明人： Kimiaki Ando

IPC分类号： H03D1/00 ,  H04B1/00 ,  H04L7/00

CPC分类号： H04B1/7085

摘要： One code is generated by combining (including addition) 2 or more codes, correlation detection method which detects the correlation by multiplying such a generated code by the reception data. In communication system based on W-CDMA method, first spreading code (a·Cp) obtained by multiplying primary synchronization code with a predetermined coefficient and second spreading code (a·Cs) obtained by multiplying secondary synchronization code with a predetermined coefficient are added. Then, the third spreading code (a·Cp+a·Cs) obtained from such an addition is multiplied by the reception data, and correlation value is obtained after integrating the multiplication results. Thus, it is determined whether the reception data has been subjected to STTD diversity.

摘要翻译： 通过组合（包括加法）2个或更多个代码产生一个代码，相关检测方法通过将这样的生成代码乘以接收数据来检测相关性。 在基于W-CDMA方式的通信系统中，添加通过将主同步码与预定系数相乘而获得的第一扩展码（a.Cp）和通过将次同步码与预定系数相乘而获得的第二扩展码（a.c）。 然后，将从这种加法得到的第三扩展码（a.Cp + a.Cs）乘以接收数据，并且在对乘法结果进行积分后获得相关值。 因此，确定接收数据是否已经经受STTD分集。

公开(公告)号：US06977956B2

公开(公告)日：2005-12-20

申请号：US09778896

申请日：2001-02-08

申请人： Kimiaki Ando ,  Hiroki Shinde

发明人： Kimiaki Ando ,  Hiroki Shinde

IPC分类号： H04B1/76 ,  H04B1/10 ,  H04B1/707 ,  H04B1/7073

CPC分类号： H04B1/7097 ,  H04B2201/70701

摘要： The pilot signal reception method of the present invention irregularly receives pilot symbols. That is, the pilot signal reception method performs irregular reception processing such as randomizing reception timings or changing reception timings according to reception situations as appropriate to reduce influences of fading. Randomization of reception timings is implemented by generating random timings using a random timing generation circuit.

摘要翻译： 本发明的导频信号接收方法不规则地接收导频符号。 也就是说，导频信号接收方法根据适合的接收情况进行诸如使接收定时随机化或者改变接收定时的不规则接收处理，以减少褪色的影响。 通过使用随机定时产生电路产生随机定时来实现接收定时的随机化。

公开(公告)号：US06352202B2

公开(公告)日：2002-03-05

申请号：US09228412

申请日：1999-01-12

申请人： Masahiro Takiguchi ,  Kiyoshi Takahashi ,  Tatsuya Hirata ,  Shigeru Date ,  Hisanobu Dobashi ,  Shinji Nishimura ,  Kimiaki Ando ,  Tadashi Sato ,  Hiromi Sato ,  Toru Miura

发明人： Masahiro Takiguchi ,  Kiyoshi Takahashi ,  Tatsuya Hirata ,  Shigeru Date ,  Hisanobu Dobashi ,  Shinji Nishimura ,  Kimiaki Ando ,  Tadashi Sato ,  Hiromi Sato ,  Toru Miura

IPC分类号： G06K708

CPC分类号： G06K7/10059 ,  G06K7/0008

摘要： A reader/writer (RW) requires identification information pieces of respective plural IC cards (A, B, C). The plural IC cards return the respective identification information pieces in response to the requirement by the reader/writer. Logical addresses are assigned to some IC cards among the plural IC cards respectively to cause the reader/writer to select them in response to the return of the identification information pieces by the plural IC cards. The IC cards selected by the reader/writer are controlled. The reader/writer cancels the assignment of the logical address to one of the selected IC cards. The logical address, the assignment of which has been canceled by the reader/writer, is assigned to an IC card among the plural IC cards to which any logical address has not been assigned yet. The IC card to which the logical address has just been assigned is controlled.

摘要翻译： 读写器（RW）需要各个IC卡（A，B，C）的识别信息。 多个IC卡响应于读/写器的要求返回各自的识别信息。 逻辑地址被分配给多个IC卡中的一些IC卡，以响应于多个IC卡返回识别信息片而使读取器/写入器选择它们。 控制由读写器选择的IC卡。 读取器/写入器将逻辑地址的分配取消到所选IC卡之一。 读取器/写入器取消了其分配的逻辑地址被分配给尚未分配任何逻辑地址的多个IC卡中的IC卡。 刚刚分配了逻辑地址的IC卡被控制。

公开(公告)号：US5999409A

公开(公告)日：1999-12-07

申请号：US10184

申请日：1998-01-21

申请人： Kimiaki Ando ,  Takehiro Ohkawa ,  Kazuo Kaneko

发明人： Kimiaki Ando ,  Takehiro Ohkawa ,  Kazuo Kaneko

IPC分类号： B42D15/10 ,  G06K19/07 ,  G06K19/077 ,  H04B5/02 ,  H05K1/16 ,  H05K1/14 ,  G06K19/067 ,  H01Q1/36

CPC分类号： G06K19/07779 ,  G06K19/07749 ,  G06K19/07783 ,  H05K1/16

摘要： The pattern line width of a coil is partially widened in a predetermined dimension and wiring patterns of a coil on the surface side and a coil on the rear side are arranged so as not to be in overlapped positions. Consequently, a direct current resistance of the coil can be reduced and an adverse influence by a self resonance of the coil on a communication can be reduced.

公开(公告)号：US06525519B2

公开(公告)日：2003-02-25

申请号：US09894107

申请日：2001-06-28

申请人： Kimiaki Ando ,  Hiroki Shinde

发明人： Kimiaki Ando ,  Hiroki Shinde

IPC分类号： G01R23167

CPC分类号： H03M1/187 ,  H03M1/18 ,  H03M1/183

摘要： An amplitude detecting circuit (1) includes a simple digital filter (2) having a structure corresponding to a part where the energy is concentrated in the full impulse response of a signal processing digital filter (3). Concretely, for example, the amplitude detecting circuit (1) (simple digital filter (2)) includes only four central taps having coefficients of large absolute values and considerably affecting on the output amplitude among sixteen taps of the signal processing digital filter (3). By the amplitude detecting circuit (1), the amplitude of an output signal of the signal processing digital filter (3) can approximately be detected.

摘要翻译： 振幅检测电路（1）包括简单数字滤波器（2），其具有对应于能量集中在信号处理数字滤波器（3）的全脉冲响应中的部分的结构。 具体地，例如，振幅检测电路（1）（简单数字滤波器（2））仅包括具有大绝对值系数的四个中心抽头，并且对信号处理数字滤波器（3）的十六个抽头之间的输出振幅有显着影响， 。 通过振幅检测电路（1），可以大致检测信号处理数字滤波器（3）的输出信号的振幅。

公开(公告)号：US5197097A

公开(公告)日：1993-03-23

申请号：US638577

申请日：1991-01-07

申请人： Yasushi Takahashi ,  Eiichi Amada ,  Kimiaki Ando ,  Masanori Miyata

发明人： Yasushi Takahashi ,  Eiichi Amada ,  Kimiaki Ando ,  Masanori Miyata

IPC分类号： H04B10/27 ,  H04B10/00 ,  H04J3/06 ,  H04L12/70 ,  H04L12/931 ,  H04Q3/52 ,  H04Q11/00 ,  H04Q11/04

CPC分类号： H04Q11/04 ,  H04J3/0605 ,  H04Q11/0001 ,  H04Q11/0066

摘要： A cell signal processing circuit is provided which is capable of precisely extracting a timing signal and a cell synchronizing signal. The cell signal processing circuit is principally composed of a signal adder circuit for adding a dummy signal comprising bit signals in a direct current balanced state to an end portion of respective inputted time series cell signals, and a separator circuit for separating and outputting the time series cell signals. Each dummy signal being composed of the same number of bits "0" and "1" is added to input signals in the form of time series cells such that signal cells are exchanged at a time of a bit "0" in the dummy signal. An optical switch apparatus using the cell signal processing circuit as an optical switch array is also provided which includes a photoelectric converter for converting the time series optical cell signal to an electric signal, a clock recovery circuit for extracting a clock signal from an output from the photoelectric converter, a cell synchronization circuit for extracting a cell synchronizing signal from the output from the photoelectric converter, and a decision circuit for deciding between signals in the output from the photoelectric converter by the use of the clock signal. The optical switch apparatus of the invention is simple and is not influenced by data loss and jitter.

公开(公告)号：US4943729A

公开(公告)日：1990-07-24

申请号：US284733

申请日：1988-12-15

申请人： Kimiaki Ando ,  Mitsuo Ooyama ,  Norio Saitou

发明人： Kimiaki Ando ,  Mitsuo Ooyama ,  Norio Saitou

IPC分类号： H01J37/302

CPC分类号： H01J37/3026

摘要： An electron beam lithography system having a contour resolving circuit for resolving original pattern data which is transferred from a host computer into contour portion pattern data and inner portion pattern data in accordance with the designated dimension, for adding flag data to enable the contour portion pattern data and the inner portion pattern data to be discriminated to the resolved pattern data, and for outputting the resolved pattern data with the flag data. By adding the flag data, the contour portion pattern data and inner portion pattern data can be easily discriminated. The operation to change the electron beam irradiation dose in accordance with the contour portion pattern and inner portion pattern can be fairly easily executed. A pattern can be drawn at a high accuracy while preventing a deformation of the drawn figure due to the proximity effect. A data processing amount in the computer can be reduced. A data transfer amount from the host computer can be also reduced. Thus, an electron beam lithography system having a high throughput can be realized.

摘要翻译： 一种具有轮廓分解电路的电子束光刻系统，用于根据所指定的尺寸，将从主计算机传送到轮廓部分图形数据和内部部分图形数据的原始图案数据解析，以便添加标志数据以使轮廓部分图形数据 以及要被区分为分辨图案数据的内部部分图案数据，并且用于使用标志数据输出分辨的图案数据。 通过添加标志数据，可以容易地区分轮廓部分图形数据和内部部分图案数据。 可以相当容易地执行根据轮廓部分图形和内部部分图案改变电子束照射剂量的操作。 可以以高精度绘制图案，同时防止由于邻近效应引起的绘制图形的变形。 可以减少计算机中的数据处理量。 也可以减少来自主机的数据传送量。 因此，可以实现具有高通量的电子束光刻系统。

公开(公告)号：US4580236A

公开(公告)日：1986-04-01

申请号：US497575

申请日：1983-05-24

申请人： Shigeo Tsujioka ,  Eiji Okamura ,  Mitsuo Ooyama ,  Kimiaki Ando ,  Seiichi Kanema ,  Mitsugu Yoneyama ,  Toshihisa Aoshima ,  Kiyoshi Umezawa

发明人： Shigeo Tsujioka ,  Eiji Okamura ,  Mitsuo Ooyama ,  Kimiaki Ando ,  Seiichi Kanema ,  Mitsugu Yoneyama ,  Toshihisa Aoshima ,  Kiyoshi Umezawa

IPC分类号： G06F9/22 ,  G06F12/02 ,  G06T11/20 ,  G09G5/20 ,  G06F3/00 ,  G09G1/06

CPC分类号： G09G5/20

摘要： A graphic display apparatus for generating a vector comprises registers for storing a value R of a vector discrimination, a positive increment P and a negative increment N, and flip-flops for storing magnitude information of .DELTA.X, .DELTA.Y, and .DELTA.X and .DELTA.Y. An address counter of a refresh memory is counted up or down in accordance with the contents of those flip-flops. A control circuit for updating the value R of the vector discrimination is also provided, so that the vector can be generated at a high speed. The registers and the flip-flops are constructed in two stages so that data for generating the next vector can be prepared while the current vector is generated.

摘要翻译： 用于产生矢量的图形显示装置包括用于存储矢量鉴别值，正增量P和负增量N的值R的寄存器和用于存储DELTA X，DELTA Y和DELTA X和DELTA的幅度信息的触发器 根据这些触发器的内容，刷新存储器的地址计数器向上或向下计数。 还提供了用于更新矢量辨别值R的控制电路，使得能够以高速生成矢量。 寄存器和触发器被构造成两个阶段，使得可以在生成当前矢量的同时准备用于生成下一个矢量的数据。