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41 条记录 (耗时 0.019 秒)

    Vector processor
    21.
    发明授权
    Vector processor 失效
    矢量处理器

    公开(公告)号：US4677547A

    公开(公告)日：1987-06-30

    申请号：US570244

    申请日：1984-01-12

    申请人： Koichiro Omoda ,  Shigeo Nagashima

    发明人： Koichiro Omoda ,  Shigeo Nagashima

    IPC分类号： G06F17/16 ,  G06F15/78 ,  G06F9/00

    CPC分类号： G06F15/8053

    摘要： At the point of time at which a segment base address is generated in current loop processing, a segment address displacement for use in the next loop processing is calculated in advance and held in one of a plurality of address registers, thereby to shorten the period of time required for address generation and to permit an overlap in the loop processing. Besides, in order to permit an overlapping in the loop processing even in a case where address registers of identical number are shared for effective utilization among different instructions, (n+1) groups of address registers are provided, and the overlapping of operations can be realized among the n successive loop processings.

    摘要翻译： 在当前循环处理中产生段基地址的时间点，预先计算用于下一循环处理的段地址位移并保存在多个地址寄存器之一中，从而缩短 产生地址所需的时间，并允许循环处理中的重叠。 此外，为了在循环处理中允许重叠，即使在不同指令之间共享用于相同数量的地址寄存器用于有效利用的情况下，提供（n + 1）个地址寄存器组，并且操作的重叠可以是 在n个连续的循环处理中实现。

    Interconnection network and crossbar switch for the same
    24.
    发明授权
    Interconnection network and crossbar switch for the same 失效
    互联网和交叉开关为一体

    公开(公告)号：US5517619A

    公开(公告)日：1996-05-14

    申请号：US203265

    申请日：1994-02-28

    申请人： Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Takehisa Hayashi ,  Teruo Tanaka ,  Shigeo Nagashima

    发明人： Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Takehisa Hayashi ,  Teruo Tanaka ,  Shigeo Nagashima

    IPC分类号： G06F13/40 ,  G06F15/173 ,  G06F13/38

    CPC分类号： G06F15/17375 ,  G06F13/4022 ,  G06F15/17381

    摘要： In a parallel computer including L=n.sub.1 .times.n.sub.2 .times. - - - .times.n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L.times.(1/n.sub.1 +1/n.sub.2 + - - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N), 0.ltoreq.i.sub.1 .ltoreq.n.sub.1 -1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2 -1; - - - , 0.ltoreq.i.sub.N ; and .ltoreq.n.sub.N -1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates (i.sub.1, i.sub.2, - - - , i.sub.k-1, i.sub.k+1, - - - , i.sub.N) of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).

    摘要翻译： 在包括L = n1xn2x - - - xnN处理器元件或以外的设备（以下由处理器元件表示）的并行计算机中，使用Lx（1 / n1 + 1 / n2 + - - + 1 / nN）交叉开关的处理器元件的互连网络 总共包括N维网格坐标（i1，i2，...，iN），0

    Data transfer network suitable for use in a parallel computer
    26.
    发明授权
    Data transfer network suitable for use in a parallel computer 失效
    适用于并行计算机的数据传输网络

    公开(公告)号：US4918686A

    公开(公告)日：1990-04-17

    申请号：US224894

    申请日：1988-07-27

    申请人： Takehisa Hayashi ,  Koichiro Omada ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

    发明人： Takehisa Hayashi ,  Koichiro Omada ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

    IPC分类号： H04L12/935 ,  H04L12/937

    CPC分类号： H04L49/3018 ,  H04L49/254 ,  H04L49/3027

    摘要： In a data transfer network of the present invention, each switch is designed such that when the partial address necessary for a given switch to determine another switch belonging to the succeeding stage, to which a packet is to be delivered from the given switch, is included in the first one of plural subpackets supplied to the given switch and each having the partial address, the given switch starts its switching operation upon arrival of the first subpacket. In a preferred embodiment, when the partial address necessary for the succeeding switch to make its switching operation is not included in the first subpacket, the partial addresses are exchanged between the subpackets by the preceding switch so that the said partial address is now included in the first subpacket.

    摘要翻译： 在本发明的数据传输网络中，每个交换机被设计成使得当给定交换机所需的部分地址被确定为属于后一级的另一交换机时，包括从给定交换机向其传送分组的部分地址 在提供给给定开关并且每个具有部分地址的多个子分组中的第一个子分组中，给定开关在第一子分组到达时开始其切换操作。 在优选实施例中，当后续交换机进行其切换操作所需的部分地址不包括在第一子分组中时，通过前一交换机在子分组之间交换部分地址，使得所述部分地址现在包括在 第一个子分组

    Processor for carrying out vector operation wherein the same vector element is used repeatedly in succession
    27.
    发明授权
    Processor for carrying out vector operation wherein the same vector element is used repeatedly in succession 失效
    用于执行矢量操作的处理器，其中相继的矢量元素被连续使用

    公开(公告)号：US4621324A

    公开(公告)日：1986-11-04

    申请号：US562224

    申请日：1983-12-16

    申请人： Yasunori Ushiro ,  Shigeo Nagashima ,  Shun Kawabe

    发明人： Yasunori Ushiro ,  Shigeo Nagashima ,  Shun Kawabe

    IPC分类号： G06F17/16 ,  G06F15/80 ,  G06F13/00

    CPC分类号： G06F15/8092

    摘要： A vector processor provided wtih a vector register to set therein vector element data having been stored in a main storage, prior to a vector operation, is disclosed in which control information indicating whether new element data is read out from the main storage to be set in one location of the vector register capable of storing one vector element data and to be latched, or vector element data having been latched is set in the above location, is set in a mask register, for each location of the vector register, and the control information is successively read out from the mask register, to set vector element data in the vector register in accordance with the read-out control information.

    摘要翻译： 向量处理器提供矢量寄存器以在其中设置已经存储在主存储器中的向量操作之前的向量元素数据，其中指示是否从主存储器读出新元素数据被设置在 对于矢量寄存器的每个位置，将能够存储一个矢量元素数据并被锁存的向量寄存器的一个位置或被锁存的向量元素数据设置在上述位置中，被设置在屏蔽寄存器中，并且控制 信息从掩模寄存器连续地读出，根据读出的控制信息在向量寄存器中设置矢量元素数据。

    Vector processor with vector data compression/expansion capability
    29.
    发明授权
    Vector processor with vector data compression/expansion capability 失效
    矢量处理器具有矢量数据压缩/扩展能力

    公开(公告)号：US4881168A

    公开(公告)日：1989-11-14

    申请号：US034950

    申请日：1987-04-06

    申请人： Yasuhiro Inagami ,  Takayuki Nakagawa ,  Yoshiko Tamaki ,  Shigeo Nagashima

    发明人： Yasuhiro Inagami ,  Takayuki Nakagawa ,  Yoshiko Tamaki ,  Shigeo Nagashima

    IPC分类号： G06F17/16 ,  G06F15/78 ,  G06T9/00

    CPC分类号： G06F9/3824 ,  G06F15/8084 ,  G06F9/30043 ,  G06T9/008

    摘要： A vector processor has a memory for storing vector data, a plurality of vector registers each capable of reading or writing plural (m) vector elements in parallel, at least one mask vector register capable of storing m mask bits in parallel, and a transfer section connected to the memory, the plurality of vector registers and the mask vector register and responsive to a store compression instruction or a load expansion instruction for transferring vector elements to or from regularly spaced address locations within the memory from or to selected storage locations of a selected vector register corresponding to valid mask bits. The transfer section includes at least one count unit connected to the mask vector register for counting a total number of valid mask bits within all of the already read out mask bits, and plural (m) access units operable concurrently and connected to the count unit and the mask vector register. Each access unit is responsive to the validity of a corresponding one within currently read out m mask bits, to a total number of valid mask bits or invalid mask bits included within the currently read m mask bits and having preceding sequential numbers of elements to that of the corresponding mask bit, and to the counted total number, and operates to generate an address of a location within the memory which holds a vector element to be transferred to a storage location corresponding to the corresponding mask bit within the selected vector register or which should receive a vector element read out from the storage location.

    摘要翻译： 矢量处理器具有用于存储矢量数据的存储器，能够并行地读取或写入多个（m）个矢量元素的多个矢量寄存器，能够并行存储m个掩码位的至少一个掩码向量寄存器，以及传送部分 连接到存储器，多个向量寄存器和掩码向量寄存器，并且响应于存储器压缩指令或负载扩展指令，用于将存储器内的规则间隔地址位置中的向量元素传送到所选择的存储器或选定的存储位置 向量寄存器对应于有效的掩码位。 传送部分包括至少一个计数单元，连接到掩模向量寄存器，用于对所有已经读出的掩码位内的有效掩码位的总数进行计数;以及多个（m）个访问单元，可同时并行连接到计数单元， 掩码向量寄存器。 每个访问单元响应于当前读出的m个掩码位内的对应的有效值，到当前读取的m个掩码位内包括的有效屏蔽位或无效掩码位的总数，并且具有先前的顺序数目的元素 对应的屏蔽位和计数的总数，并且操作以产生存储器内的位置的地址，该地址保存要传送到与所选择的向量寄存器内的对应掩码位相对应的存储位置的向量元素，或者应当 接收从存储位置读出的向量元素。

    Processor for VLIW instruction
    30.
    发明授权
    Processor for VLIW instruction 失效
    处理器用于VLIW指令

    公开(公告)号：US6044450A

    公开(公告)日：2000-03-28

    申请号：US824486

    申请日：1997-03-27

    申请人： Yuji Tsushima ,  Yoshikazu Tanaka ,  Yoshiko Tamaki ,  Masanao Ito ,  Kentaro Shimada ,  Yonetaro Totsuka ,  Shigeo Nagashima

    发明人： Yuji Tsushima ,  Yoshikazu Tanaka ,  Yoshiko Tamaki ,  Masanao Ito ,  Kentaro Shimada ,  Yonetaro Totsuka ,  Shigeo Nagashima

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F7/00

    CPC分类号： G06F9/30025 ,  G06F9/30178 ,  G06F9/3853

    摘要： Each small instruction in a VLIW instruction (long instruction) is added with the number of NOP instructions which succeed the small instruction, and these NOP instructions are deleted from the succeeding long instruction. A plurality of long instructions are therefore time-compressed. Thereafter, a plurality of small instructions in each long instruction are divided into a plurality of groups, and a combination of operation codes (OP codes) of small instructions in each group is replaced by a group code to generate a compressed, grouped instruction. Each long instruction is therefore space-compressed. An instruction expanding unit has an instruction expanding circuit for each grouped instruction. Each instruction expanding circuit expands one grouped instruction in a long instruction, generates a group of small instructions represented by the grouped instruction, and supplies the group of generated small instructions to respective function units via a decode unit. In this case, each instruction expanding circuit supplies after each small instruction NOP instructions same in number as that designated by a NOP number associated with each small instruction in this grouped instruction.

    摘要翻译： VLIW指令（长指令）中的每个小指令都加上小指令成功的NOP指令数，并从后续长指令中删除这些NOP指令。 因此，多个长指令被时间压缩。 此后，每个长指令中的多个小指令被分成多个组，并且组中的小指令的操作码（OP代码）的组合被组代码替换以生成压缩的分组指令。 因此，每个长指令都是空间压缩的。 指令扩展单元具有用于每个分组指令的指令扩展电路。 每个指令扩展电路在长指令中扩展一个分组指令，生成由分组指令表示的一组小指令，并且经由解码单元将所生成的小指令组提供给各个功能单元。 在这种情况下，每个指令扩展电路在与分组指令中的每个小指令相关联的NOP号指定的每个小指令NOP指令之后提供数量相同的每个指令扩展电路。