公开(公告)号：US20050200511A1

公开(公告)日：2005-09-15

申请号：US11060306

申请日：2005-02-18

申请人： Atsushi Wada ,  Kuniyuki Tani ,  Shigeto Kobayashi

发明人： Atsushi Wada ,  Kuniyuki Tani ,  Shigeto Kobayashi

IPC分类号： H03M1/14 ,  H03M1/12

CPC分类号： H03M1/164 ,  H03M1/162

摘要： A first analog-digital converter circuit in a preceding stage converts an input analog signal into a digital value and retrieves the higher 4 bits. A second analog-digital converter circuit in a subsequent stage converts an input analog signal into a digital value and retrieves 3 bits including the 5th through 6th highest bits and a redundant bit, 3 bits including the 7th through 8th highest bits and a redundant bit, and 3 bits including the 9th through 10th highest bits and a redundant bit. Thus, the number of bits produced by conversion by the second analog-digital converter circuit in the subsequent stage of a cyclic type is configured to be smaller than the number of bits produced by conversion by the first analog-digital converter circuit in the preceding stage.

摘要翻译： 前一级的第一模数转换器电路将输入的模拟信号转换为数字值，并检索较高的4位。 后续阶段的第二模拟数字转换器电路将输入的模拟信号转换为数字值，并且检索包括第5至第6高位的3位和冗余位，包括第7位至第8位的3位和冗余位， 并且包括第9到第10最高位的3位和冗余位。 因此，通过第二模拟数字转换器电路在循环类型的后续阶段的转换而产生的位数被配置为小于由前一级中的第一模数转换器电路的转换产生的位数 。

公开(公告)号：US20050068219A1

公开(公告)日：2005-03-31

申请号：US10945924

申请日：2004-09-22

申请人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada ,  Takafumi Nakamori

发明人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada ,  Takafumi Nakamori

IPC分类号： H03F1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/14 ,  H03M1/16 ,  H03M1/36 ,  H03M1/38 ,  H03M1/40

CPC分类号： H03M1/06 ,  H03M1/162 ,  H03M1/365

摘要： A cyclic AD converter having a conversion processing speed or conversion accuracy designed no higher than necessary. In the AD converter, an input analog signal is held by a sample-and-hold circuit, and converted into a digital value by an AD conversion circuit. A DA conversion circuit converts the digital value output from the AD conversion circuit into an analog value. A subtractor circuit outputs the difference between the analog value output from the AD conversion circuit and the analog value held in the sample-and-hold circuit. An amplifier circuit amplifies the output of the subtractor circuit, and feeds back the resultant to the sample-and-hold circuit and the AD conversion circuit. In the course of this feedback-based cyclic processing, an amplification control circuit changes the gain of the amplifier circuit in accordance with the progress of the circulation.

摘要翻译： 一种循环AD转换器，其转换处理速度或转换精度设定为不必要。 在AD转换器中，输入模拟信号由采样保持电路保持，并由AD转换电路转换为数字值。 DA转换电路将从AD转换电路输出的数字值转换为模拟值。 减法器电路输出从AD转换电路输出的模拟值与保持在采样保持电路中的模拟值之间的差。 放大器电路放大减法器电路的输出，并将结果反馈到采样保持电路和AD转换电路。 在基于反馈的循环处理的过程中，放大控制电路根据循环的进行改变放大器电路的增益。

公开(公告)号：US20060279447A1

公开(公告)日：2006-12-14

申请号：US11506778

申请日：2006-08-21

申请人： Atsushi Wada ,  Kuniyuki Tani ,  Shigeto Kobayashi

发明人： Atsushi Wada ,  Kuniyuki Tani ,  Shigeto Kobayashi

IPC分类号： H03M1/12

CPC分类号： H01L29/1083 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7833 ,  H03M1/005 ,  H03M1/007 ,  H03M1/162 ,  H03M1/167

摘要： The present invention provides a widely general-purpose A/D converting device. The A/D converting device comprises multiple signal conversion units each of which include: an A/D converter for converting an input analog signal into a digital signal with a predetermined number of bits; a D/A converter for converting the output from the A/D converter into an analog signal; a subtracter for subtracting the output signal from the D/A converter, from the input analog signal; and an amplifier for amplifying the output signal from the subtracter. The A/D converting device has a configuration wherein the signal conversion units are arrayed in multiple rows and columns. This allows the user to realize an A/D converting device having various types and levels of performance by making various combinations of the signal conversion units without change of the layout of the signal conversion units.

公开(公告)号：US07061420B2

公开(公告)日：2006-06-13

申请号：US11072297

申请日：2005-03-07

申请人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

发明人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

IPC分类号： H03M1/12

CPC分类号： H03M1/167

摘要： A first amplifier circuit samples and amplifies an input analog signal by a gain of 0.8 and outputs the amplified signal to a first subtracter circuit. A first analog-digital converter circuit converts the input analog signal into a digital value so as to retrieve the higher 4 bits. A first digital-analog converter circuit converts the digital value produced by conversion by the first analog-digital converter circuit into an analog value. The first subtracter circuit subtracts an output analog signal from the first digital-analog converter circuit from an output analog signal from the first amplifier circuit. The output analog signal from the first digital-analog converter circuit is amplified by a gain of 0.8. By setting the gain of the first amplifier circuit to be below 1, an input voltage range is extended.

摘要翻译： 第一放大器电路以0.8的增益对输入的模拟信号进行采样和放大，并将放大的信号输出到第一减法器电路。 第一模拟数字转换器电路将输入的模拟信号转换为数字值，以便检索较高的4位。 第一数模转换器电路将由第一模数转换器电路的转换产生的数字值转换为模拟值。 第一减法器电路从第一放大电路的输出模拟信号中减去来自第一数模转换器电路的输出模拟信号。 来自第一数模转换器电路的输出模拟信号以0.8的增益放大。 通过将第一放大器电路的增益设置为低于1，可以延长输入电压范围。

公开(公告)号：US20050168369A1

公开(公告)日：2005-08-04

申请号：US11047706

申请日：2005-02-02

申请人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

发明人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

IPC分类号： H03M1/14 ,  H03M1/16 ,  H03M1/34

CPC分类号： H03M1/167 ,  H03M1/162

摘要： A first amplifier circuit amplifies an input signal by a factor of α. A first AD converter circuit is configured at an LSB voltage of VA and converts an input analog signal into a digital value of arbitrary N1 bits. A first DA converter circuit converts the digital value output from the first AD converter circuit into an analog signal. A subtracter circuit subtracts an output of the first DA converter circuit from an output of the first subtracter circuit. A second amplifier circuit amplifies an output of the subtracter circuit by a factor of β. A second AD converter is configured at an LSB voltage of VB and converts an input analog signal into a digital value of arbitrary N2 bits. In this circuit, the relation VA*α*β=VB*2N2 holds.

摘要翻译： 第一放大器电路以α的因子放大输入信号。 第一AD转换器电路配置为VA的LSB电压，并将输入的模拟信号转换成任意N 1位的数字值。 第一DA转换器电路将从第一AD转换器电路输出的数字值转换为模拟信号。 减法电路从第一减法器电路的输出中减去第一DA转换器电路的输出。 第二放大器电路将减法器电路的输出放大倍数为β。 第二AD转换器配置为VB的LSB电压，并将输入模拟信号转换为任意N 2位的数字值。 在该电路中，VA *α*β= VB * 2 N 2的关系成立。

公开(公告)号：US06900749B2

公开(公告)日：2005-05-31

申请号：US10663984

申请日：2003-09-17

申请人： Kuniyuki Tani ,  Atsushi Wada ,  Shigeto Kobayashi

发明人： Kuniyuki Tani ,  Atsushi Wada ,  Shigeto Kobayashi

IPC分类号： H03M1/10 ,  H03M1/16

CPC分类号： H03M1/1038 ,  H03M1/167

摘要： Digital signals of the most significant bit to the least significant bit are supplied to a digital calibration operation unit from a redundancy correction circuit, and an intermediate high order 2-bit digital signal is supplied to a correction value selection circuit. A DC control signal is supplied to the correction value selection circuit. A plurality of groups of correction values corresponding to the values of the intermediate high order 2-bit digital signal are stored in advance in a correction value ROM. The correction value selection circuit reads out a correction value from the correction value ROM based on the DC control signal and the intermediate high order 2-bit digital signal. The digital calibration operation unit adds the correction value AM to the digital signals of the most significant bit to the least significant bit, and outputs a resulting value as a digital output value.

摘要翻译： 将最高有效位到最低有效位的数字信号从冗余校正电路提供给数字校准操作单元，并且中间高阶2位数字信号被提供给校正值选择电路。 直流控制信号被提供给校正值选择电路。 对应于中间高阶2位数字信号的值的多组校正值被预先存储在校正值ROM中。 校正值选择电路基于DC控制信号和中间高阶2位数字信号从校正值ROM读出校正值。 数字校准操作单元将校正值AM添加到最高有效位的数字信号到最低有效位，并将结果值作为数字输出值输出。

公开(公告)号：US07745776B2

公开(公告)日：2010-06-29

申请号：US11864286

申请日：2007-09-28

申请人： Atsushi Wada ,  Kuniyuki Tani ,  Hajime Takashima

发明人： Atsushi Wada ,  Kuniyuki Tani ,  Hajime Takashima

IPC分类号： H01L31/062

CPC分类号： H04N5/235 ,  H04N5/335 ,  H04N5/35509 ,  H04N5/374 ,  H04N5/37452

摘要： In a photo detecting apparatus, a first capacitance is caused by a photo detecting element and the first capacitance is charged or discharged by current flowing through the photo detecting element. A second capacitance is connected in parallel with the photo detecting element, and the second capacitance charges or discharges an electric charge overflowing from the first capacitance. A current control element is connected to a terminal of the second capacitance on a side where the electric charge flows in, and the current control element delivers a current to cancel part of an electric charge when the electric charge overflowing from the first capacitance is stored in the second capacitance.

摘要翻译： 在光检测装置中，由光检测元件引起第一电容，并且通过流过光检测元件的电流对第一电容进行充电或放电。 第二电容与光检测元件并联连接，第二电容对从第一电容溢出的电荷进行充电或放电。 电流控制元件连接到电荷流入侧的第二电容的端子，并且当从第一电容溢出的电荷被存储在电流控制元件中时，电流控制元件输出电流以消除部分电荷 第二电容。

公开(公告)号：US20080067325A1

公开(公告)日：2008-03-20

申请号：US11858583

申请日：2007-09-20

申请人： Kuniyuki Tani ,  Hajime Takashima ,  Atsushi Wada

发明人： Kuniyuki Tani ,  Hajime Takashima ,  Atsushi Wada

IPC分类号： H01L27/144

CPC分类号： H04N5/235 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14656 ,  H04N5/3559 ,  H04N5/3591 ,  H04N5/3594 ,  H04N5/374

摘要： A plurality of pixel circuits, provided with a plurality of photo detecting elements, respectively, cause photocurrent corresponding to an incident light. The pixel circuits are placed on intersections of a plurality of data lines and scanning lines, respectively. A second capacitance charges and discharges an electric charge overflowing from a first capacitance caused by the photo detecting element. Each second capacitance is shared by a plurality of pixel circuits. A plurality of pixel circuits sharing the second capacitance are controlled so that exposure periods of the pixel circuits do not overlap with one another.

摘要翻译： 分别具有多个光检测元件的多个像素电路分别引起与入射光对应的光电流。 像素电路分别放置在多条数据线和扫描线的交点上。 第二电容对由光检测元件引起的第一电容溢出的电荷进行放电。 每个第二电容由多个像素电路共享。 控制共享第二电容的多个像素电路，使得像素电路的曝光周期彼此不重叠。

公开(公告)号：US20050270215A1

公开(公告)日：2005-12-08

申请号：US11140964

申请日：2005-06-01

申请人： Atsushi Wada ,  Kuniyuki Tani

发明人： Atsushi Wada ,  Kuniyuki Tani

IPC分类号： H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/18

CPC分类号： H03M1/181 ,  H03M1/0695 ,  H03M1/167

摘要： A DSP calculates time integration of the light amount received by a CCD, using an input image. Determination is made regarding whether or not the light amount is equal to or smaller than a predetermined threshold. In a case that the light amount is equal to or smaller than the predetermined threshold, the DSP outputs a control signal to an AD converter for operation in the 8-bit mode. In a case that the light amount is greater than the threshold, the DSP outputs a control signal to the AD converter for operation in the 10-bit mode. The AD converter has a function of dynamic adjustment of conversion bits according to control from the DSP.

摘要翻译： DSP使用输入图像计算由CCD接收的光量的时间积分。 确定光量是否等于或小于预定阈值。 在光量等于或小于预定阈值的情况下，DSP将控制信号输出到AD转换器，以在8位模式下操作。 在光量大于阈值的情况下，DSP向AD转换器输出控制信号，以在10位模式下操作。 根据DSP的控制，AD转换器具有转换位的动态调整功能。

公开(公告)号：US06882297B2

公开(公告)日：2005-04-19

申请号：US10808566

申请日：2004-03-25

申请人： Atsushi Wada ,  Kuniyuki Tani

发明人： Atsushi Wada ,  Kuniyuki Tani

IPC分类号： H03M1/44 ,  H03M1/00 ,  H03M1/12 ,  H03M1/14 ,  H03M1/16 ,  H03M1/38 ,  H03M1/46 ,  H03M1/60

CPC分类号： H03M1/002 ,  H03M1/167

摘要： A multi-stage pipelined AD converter has n stages of conversion units, such as a first conversion unit, a second conversion unit, an (n−1)th conversion unit, and an nth conversion unit, which successively convert an analog signal into a digital signal each by several bits starting from the most significant bit. Each of the converted digital signals of several bits is combined in a digital output circuit. A first voltage source supplies a higher voltage than a second voltage source. The first voltage source supplies a high voltage to the first stage or the first conversion unit, while the second voltage source supplies a low voltage to the second and subsequent stages of the second conversion unit to the nth conversion unit which require a lower analog accuracy.

摘要翻译： 多级流水线AD转换器具有n级转换单元，例如第一转换单元，第二转换单元，第（n-1）转换单元和第n转换单元，其将模拟信号连续地转换为 数字信号每个从最高有效位开始几位。 在数字输出电路中组合了数位转换的数字信号。 第一电压源提供比第二电压源更高的电压。 第一电压源向第一级或第一转换单元提供高电压，而第二电压源将第二转换单元的第二级和后级提供低电压到第n个转换单元，这需要较低的模拟精度。