公开(公告)号：US06316341B1

公开(公告)日：2001-11-13

申请号：US09510971

申请日：2000-02-21

Applicant: Kun-Chi Lin

Inventor： Kun-Chi Lin

IPC: H01L2122

CPC classification number: H01L27/10873 ,  H01L27/1203

Abstract: A method for forming a cell passes transistor in DRAM process disclosed. In one embodiment, the present invention provides a MOS structure, which can reduce junction leakage for P/N junction and increase the refreshes time capability. A method for DRAM fabrication comprises providing a semiconductor substrate having at least an isolation device therein. The isolation device defines an active area adjacent thereto on the semiconductor substrate. A first photoresist layer is formed on the semiconductor substrate, which exposes the active area in a first direction. The first conductive ions are implanted to form a well region in the semiconductor substrate, and the second conductive ions are implanted to form a field implant region in the semiconductor substrate. The third conductive ions are implanted to form a punchthrough implant region in the semiconductor substrate. Then the first photoresist layer is removed, and a second photoresist layer is formed on the semiconductor substrate. The second photoresist layer exposes the active area in a second direction different from the first direction. The fourth conductive ions are implanted to form a threshold implant region, and then the second photoresist layer is removed.

Abstract translation: 用于形成单元的方法在所公开的DRAM工艺中通过晶体管。 在一个实施例中，本发明提供一种MOS结构，其可以减少P / N结的结泄漏并增加刷新时间能力。 一种用于DRAM制造的方法包括提供其中至少具有隔离装置的半导体衬底。 隔离装置在半导体衬底上限定与其相邻的有源区。 第一光致抗蚀剂层形成在半导体衬底上，其在第一方向上暴露有源区。 注入第一导电离子以在半导体衬底中形成阱区，并且注入第二导电离子以在半导体衬底中形成场注入区。 植入第三导电离子以在半导体衬底中形成穿通注入区域。 然后去除第一光致抗蚀剂层，并且在半导体衬底上形成第二光致抗蚀剂层。 第二光致抗蚀剂层在与第一方向不同的第二方向上暴露有源区。 植入第四导电离子以形成阈值注入区域，然后去除第二光致抗蚀剂层。

公开(公告)号：US06238974B1

公开(公告)日：2001-05-29

申请号：US09475212

申请日：1999-12-29

Applicant: Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

IPC: H01L218242

CPC classification number: H01L28/84 ,  H01L21/76895 ,  H01L27/10852

Abstract: A process of fabricating a bottom electrode for the storage capacitors of DRAM is disclosed. The process includes first forming an insulation layer on the surface of the device substrate, with the insulation layer patterned to form a contact opening that exposes a source/drain region of the memory cell transistor. A first conductive layer then covers the insulation layer and fills into the contact opening, with the first conductive layer contacting the exposed source/drain region. A native oxide layer is then formed on the surface of the first conductive layer. A second electrically conductive layer is then formed and patterned to form a recess substantially above the location of the contact opening in the insulation layer. A layer of HSG—Si then covers the surface of the second conductive layer and the surface of the recess, and the HSG—Si layer and the second conductive layer are patterned to form the bottom electrode of the capacitor. The recess and its covering HSG—Si layer increase the effective surface area of the bottom electrode of the capacitor.

Abstract translation: 公开了制造用于DRAM的存储电容器的底部电极的工艺。 该方法包括首先在器件衬底的表面上形成绝缘层，其中图案化绝缘层以形成暴露存储单元晶体管的源/漏区的接触开口。 然后，第一导电层覆盖绝缘层并填充到接触开口中，第一导电层与暴露的源极/漏极区接触。 然后在第一导电层的表面上形成自然氧化物层。 然后形成第二导电层并图案化以形成基本上在绝缘层中的接触开口位置上方的凹部。 然后，HSG-Si层覆盖第二导电层的表面和凹部的表面，并且对HSG-Si层和第二导电层进行图案化以形成电容器的底部电极。 凹槽及其覆盖的HSG-Si层增加了电容器底部电极的有效表面积。

公开(公告)号：US06200904B1

公开(公告)日：2001-03-13

申请号：US09323546

申请日：1999-06-01

Applicant: Wayne Tan ,  Gwo-Shii Yang ,  Kun-Chi Lin

Inventor： Wayne Tan ,  Gwo-Shii Yang ,  Kun-Chi Lin

IPC: H01L21302

CPC classification number: H01L21/76831 ,  H01L21/76804 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

Abstract: The present invention relates to a method of forming a contact hole of a DRAM on the semiconductor wafer. The semiconductor wafer comprises a substrate, a first dielectric layer, two bit lines on the first dielectric layer, a second dielectric layer, and a photo-resist layer comprising an opening to define the pattern of the contact hole. The method comprises performing a first anisotropic etching process to vertically remove a portion of the two dielectric layers and two bit lines to grossly form the contact hole, removing the photo-resist layer in its entirety, performing a thermal oxidation to form a silicon oxide layer on the side walls of the two bit lines, then forming a silicon nitride layer on the surface of the contact hole, and performing a dry etching to remove the silicon nitride layer. There is a silicon oxide layer and a silicon nitride layer between the bit line and the contact hole, and the contact area of the contact hole will not be reduced.

Abstract translation: 本发明涉及在半导体晶片上形成DRAM的接触孔的方法。 半导体晶片包括基板，第一介电层，第一电介质层上的两个位线，第二电介质层和包含用于限定接触孔的图案的开口的光致抗蚀剂层。 该方法包括执行第一各向异性蚀刻工艺以垂直去除两个电介质层和两个位线的一部分，以大致形成接触孔，完全去除光致抗蚀剂层，进行热氧化以形成氧化硅层 在两个位线的侧壁上，然后在接触孔的表面上形成氮化硅层，并进行干蚀刻以除去氮化硅层。 位线和接触孔之间有一个氧化硅层和一个氮化硅层，接触孔的接触面积不会减小。

公开(公告)号：US6150278A

公开(公告)日：2000-11-21

申请号：US357236

申请日：1999-07-20

Applicant: Wayne Tan ,  Kun-Chi Lin

Inventor： Wayne Tan ,  Kun-Chi Lin

IPC: H01L21/02 ,  H01L21/8242

CPC classification number: H01L27/10852 ,  H01L27/10885 ,  H01L28/84

Abstract: An improved method of fabricating a node capacitor for a dynamic random access memory (DRAM) process is disclosed. The process includes depositing a first interpoly dielectric (IPD1) layer over a substrate, patterning a first photoresist layer on the first interpoly dielectric layer, thereby defining a trench. A trench is etched in the first interpoly dielectric layer using the first photoresist layer as a mask. A first polysilicon layer is deposited on the first interpoly dielectric layer. The first polysilicon layer is etched to expose the first interpoly dielectric layer, then forming a landing pad over the substrate. In order to a polycide layer and a second interpoly dielectric (IPD2) layer are deposited, patterning a second photoresist layer, thereby defining a bit line structure. A bit line structure is formed, then depositing a spacer on the bit line structure. A second polysilicon layer is deposited, patterning a third photoresist layer, thereby defining a bottom electrode. A bottom electrode is formed, then depositing a thin NO (silicon nitride-silicon oxide) dielectric layer on the bottom electrode. An addition step is performed before forming the thin NO dielectric layer on the bottom electrode. In this additional step, a hemispherical grain (HSG) polysilicon layer is formed on the second polysilicon layer. This advantage is used to the hemispherical grain polysilicon layer increasing the area of a node capacitor. A third polysilicon layer is deposited completely covering the thin NO dielectric layer to form a top electrode.

Abstract translation: 公开了一种制造用于动态随机存取存储器（DRAM）工艺的节点电容器的改进方法。 该方法包括在衬底上沉积第一层间电介质（IPD1）层，对第一层间电介质层上的第一光致抗蚀剂层进行构图，从而限定沟槽。 使用第一光致抗蚀剂层作为掩模，在第一互聚电介质层中蚀刻沟槽。 第一多晶硅层沉积在第一互聚电介质层上。 蚀刻第一多晶硅层以暴露第一多余介电层，然后在衬底上形成着色焊盘。 为了沉积多晶硅化物层和第二多晶硅电介质（IPD2）层，图案化第二光致抗蚀剂层，从而限定位线结构。 形成位线结构，然后在位线结构上沉积间隔物。 沉积第二多晶硅层，图案化第三光致抗蚀剂层，从而限定底部电极。 形成底部电极，然后在底部电极上沉​​积薄的NO（氮化硅 - 氧化硅）电介质层。 在底电极上形成薄的NO电介质层之前进行添加步骤。 在该附加步骤中，在第二多晶硅层上形成半球状晶粒（HSG）多晶硅层。 这个优点用于半球形晶粒多晶硅层增加节点电容器的面积。 沉积第三多晶硅层完全覆盖薄的NO介电层以形成顶部电极。

公开(公告)号：US6136642A

公开(公告)日：2000-10-24

申请号：US220146

申请日：1998-12-23

Applicant: Wayne Tan ,  Kun-Chi Lin

Inventor： Wayne Tan ,  Kun-Chi Lin

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10885 ,  H01L27/10814

Abstract: A method of fabricating a dynamic random access memory includes forming a dummy layer over the isolation layer, in which the dummy layer has a higher etching selectivity than oxide. A dielectric layer is applied to isolate the bit lines. Then, a passivation layer is formed over the entire structure and a node contact opening is formed thereon. A liner oxide layer is then formed in the node contact opening to isolate the bit lines and the electrode of the capacitor. The node contact opening has a larger misalignment tolerance.

Abstract translation: 制造动态随机存取存储器的方法包括在隔离层上形成虚设层，其中虚设层具有比氧化物更高的蚀刻选择性。 施加电介质层以隔离位线。 然后，在整个结构上形成钝化层，并在其上形成节点接触开口。 然后在节点接触开口中形成衬垫氧化物层，以隔离电容器的位线和电极。 节点接触开口具有较大的不对准公差。

公开(公告)号：US6096594A

公开(公告)日：2000-08-01

申请号：US188652

申请日：1998-11-09

Applicant: Kun-Chi Lin ,  Chia-Wen Liang ,  Hal Lee

Inventor： Kun-Chi Lin ,  Chia-Wen Liang ,  Hal Lee

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/8249

CPC classification number: H01L27/10852 ,  H01L27/10814 ,  H01L27/10873

Abstract: The present invention provides a fabricating method and structure of a dynamic random access memory. In this method, a substrate having a transistor thereon is provided. A bit line is formed on the substrate. The bit line is electrically coupled with the transistor through a contact hole. A second dielectric layer having a node contact opening is formed on the bit line. An etching step is performed to etch the bit line. A concave surface is formed on the sidewall of the bit line. Spacer layers are formed on the sidewalls of the node contact opening. Each spacer layer is used to insulate the concave surface. Thus, from the top-view layout, a portion of the node contact opening can overlap with the bit line. Thus, the size of DRAM is effectively reduced.

Abstract translation: 本发明提供一种动态随机存取存储器的制造方法和结构。 在该方法中，设置有具有晶体管的基板。 在基板上形成位线。 位线通过接触孔与晶体管电耦合。 具有节点接触开口的第二电介质层形成在位线上。 执行蚀刻步骤来蚀刻位线。 在位线的侧壁上形成凹面。 间隔层形成在节点接触开口的侧壁上。 每个间隔层用于使凹面绝缘。 因此，从顶视图布局，节点接触开口的一部分可以与位线重叠。 因此，DRAM的尺寸被有效地减小。

公开(公告)号：US6074955A

公开(公告)日：2000-06-13

申请号：US189116

申请日：1998-11-09

Applicant: Kevin Lin ,  Chia-Wen Liang ,  Kun-Chi Lin

Inventor： Kevin Lin ,  Chia-Wen Liang ,  Kun-Chi Lin

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L27/10852 ,  H01L21/76816 ,  H01L21/76897 ,  H01L21/31144 ,  H01L27/10873 ,  H01L27/10882

Abstract: A method of fabricating a node contact window. A substrate having devices and a first dielectric layer is provided. Bit lines having spacer are formed on the first dielectric layer and a second is formed on the first dielectric layer. A hard material layer is then formed on the second dielectric layer. An opening is formed within the second dielectric layer to expose the spacer and the first dielectric layer. A polysilicon spacer is then formed on the sidewalls of the opening. A node contact window is formed by etching through the first dielectric layer to expose the substrate.

Abstract translation: 一种制造节点接触窗口的方法。 提供具有器件和第一介电层的衬底。 具有间隔物的位线形成在第一电介质层上，第二电极形成在第一电介质层上。 然后在第二电介质层上形成硬质材料层。 在第二电介质层内形成开口以露出间隔物和第一介电层。 然后在开口的侧壁上形成多晶硅间隔物。 通过蚀刻穿过第一电介质层形成节点接触窗，露出衬底。

公开(公告)号：US5861333A

公开(公告)日：1999-01-19

申请号：US738328

申请日：1996-10-25

Applicant: Kun-Chi Lin

Inventor： Kun-Chi Lin

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/7883

Abstract: The present invention includes forming a first field oxide region (FOX) on a substrate. Buried N.sup.+ regions are then formed. Subsequently, a plurality of second FOX regions are formed. A tunneling window region between the second FOX regions is narrowed by the formation of the second FOX regions. Then a tunnel oxide is formed on the substrate. A first polysilicon layer is deposited on the first FOX, the second FOXs, the gate oxide, the tunnel oxide and the substrate. An etching step is used to define the floating gate. A dielectric layer is formed on the floating gate. A second polysilicon layer is then formed on the dielectric layer. The second polysilicon layer and the dielectric layer are etched. An ion implantation step is used to form source and drain of the gate.

Abstract translation: 本发明包括在基板上形成第一场氧化物区域（FOX）。 然后形成掩埋的N +区。 随后，形成多个第二FOX区域。 第二FOX区域之间的隧道窗口区域由于形成第二FOX区域而变窄。 然后在衬底上形成隧道氧化物。 第一多晶硅层沉积在第一FOX，第二FOX，栅极氧化物，隧道氧化物和衬底上。 蚀刻步骤用于限定浮动栅极。 在浮栅上形成介电层。 然后在电介质层上形成第二多晶硅层。 蚀刻第二多晶硅层和电介质层。 离子注入步骤用于形成栅极的源极和漏极。

公开(公告)号：US07173833B2

公开(公告)日：2007-02-06

申请号：US10908159

申请日：2005-04-29

Applicant: Kun-Chi Lin ,  Youjun Zhang ,  Qinggang Kong ,  Junshan Lou ,  Hongjian Gan

Inventor： Kun-Chi Lin ,  Youjun Zhang ,  Qinggang Kong ,  Junshan Lou ,  Hongjian Gan

IPC: H02M7/23

CPC classification number: H02M3/285 ,  H02M2001/0032 ,  Y02B70/16

Abstract: A power supply device and an operating method thereof are provided. The power supply device includes a main converter and an auxiliary converter. The main converter includes a power factor corrector (PFC), a first capacitor that connects in parallel with the PFC and a DC/DC converter that connects in parallel with the first capacitor. The auxiliary converter is connected in parallel to the main converter. When the power supply device operates in a normal mode, the main converter and the auxiliary converter together provide a first output to an output load. When the power supply device is in a standby mode, the DC/DC converter is turned off so that only the auxiliary converter provides a second output to the output load. Meanwhile, the PFC is in operation to maintain the voltage of the first capacitor in order to meet the demand of the output dynamic response of the main converter.

Abstract translation: 提供电源装置及其操作方法。 电源装置包括主转换器和辅助转换器。 主转换器包括功率因数校正器（PFC），与PFC并联连接的第一电容器和与第一电容器并联连接的DC / DC转换器。 辅助转换器与主转换器并联连接。 当电源装置在正常模式下工作时，主转换器和辅助转换器一起向输出负载提供第一输出。 当电源设备处于待机模式时，DC / DC转换器关闭，只有辅助转换器向输出负载提供第二个输出。 同时，为了满足主转换器的输出动态响应的要求，PFC正在运行以维持第一电容器的电压。

公开(公告)号：US06432772B1

公开(公告)日：2002-08-13

申请号：US09682402

申请日：2001-08-30

Applicant: King-Lung Wu ,  Kun-Chi Lin

Inventor： King-Lung Wu ,  Kun-Chi Lin

IPC: H01L218242

CPC classification number: H01L28/84 ,  H01L21/28525 ,  H01L28/75 ,  H01L28/91 ,  Y10S438/964

Abstract: An isolation layer is formed on a substrate of a semiconductor wafer. At least one recess is formed in the isolation layer by way of a photo-etching-process. A two stage in-situ doped deposition process is then performed to form a first doped amorphous silicon (&agr;-Si) layer and a second doped amorphous silicon (&agr;-Si) layer doping concentration of the second doped amorphous silicon (&agr;-Si) layer being less than that of the first doped amorphous silicon layer. A dielectric layer is formed to fill the recess, and a planarization process removes portions of the second doped amorphous silicon layer, the first doped amorphous silicon layer and the dielectric layer on the surface of the isolation layer. Finally, the dielectric layer and the isolation layer are removed, and a hemi-spherical grain (HSG) process is performed to form a rough surface with a plurality of hemi-spherical grains on the surface of the second doped amorphous silicon layer.

Abstract translation: 在半导体晶片的基板上形成隔离层。 通过光蚀刻工艺在隔离层中形成至少一个凹部。 然后进行两级原位掺杂沉积工艺以形成第二掺杂非晶硅（α-Si）层和第二掺杂非晶硅（α-Si）层掺杂浓度的第二掺杂非晶硅（α-Si） 层小于第一掺杂非晶硅层的层。 形成介电层以填充凹部，并且平坦化处理去除隔离层表面上的第二掺杂非晶硅层，第一掺杂非晶硅层和电介质层的部分。 最后，去除电介质层和隔离层，并且在第二掺杂非晶硅层的表面上执行半球形晶粒（HSG）工艺以形成具有多个半球形晶粒的粗糙表面。