公开(公告)号：US06417065B1

公开(公告)日：2002-07-09

申请号：US09718190

申请日：2000-11-20

申请人： King-Lung Wu ,  Kun-Chi Lin

发明人： King-Lung Wu ,  Kun-Chi Lin

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L21/76802 ,  H01L21/76897 ,  H01L27/10885 ,  H01L28/91

摘要： A method of fabricating a bottom electrode is described. A substrate having a conductive layer therein is provided. A first dielectric layer is formed over the substrate. A conductive plug is formed through the first dielectric layer to electrically couple with the conductive layer. A cap layer is formed over the substrate to cover the conductive plug. An isolation layer is formed over the cap layer. A plurality of bit lines is formed over the isolation layer. A second dielectric layer is formed over the isolation layer. A node contact opening is formed through the second dielectric layer, the bit lines and the isolation layer to expose the cap layer. A conformal isolation layer is formed over the substrate to partially fill the contact node opening. A third dielectric layer having an opening is formed over the substrate. The opening is aligned with the node contact opening. An etching step is performed to remove a portion of the conformal isolation layer exposed by the opening and the cap layer. An isolation spacer remaining from the conformal isolation layer is formed on a sidewall of the contact node opening. A conformal conductive layer is formed in the opening and the node contact opening to make contact with the conductive plug. The third dielectric layer is removed.

摘要翻译： 描述制造底部电极的方法。 提供其中具有导电层的基板。 第一电介质层形成在衬底上。 导电插塞通过第一介电层形成，以与导电层电耦合。 在衬底上形成覆盖导电插塞的覆盖层。 在盖层上方形成隔离层。 多个位线形成在隔离层上。 在隔离层上形成第二电介质层。 通过第二介电层，位线和隔离层形成节点接触开口以露出盖层。 在衬底上形成保形隔离层以部分地填充接触节点开口。 在衬底上形成具有开口的第三电介质层。 开口与节点接触开口对齐。 执行蚀刻步骤以去除由开口和盖层暴露的一部分共形隔离层。 从保形隔离层剩余的隔离间隔物形成在接触节点开口的侧壁上。 在开口和节点接触开口中形成共形导电层以与导电插塞接触。 去除第三电介质层。

公开(公告)号：US06225160B1

公开(公告)日：2001-05-01

申请号：US09295067

申请日：1999-04-20

申请人： Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

发明人： Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/84

摘要： A method of manufacturing a bottom electrode of a capacitor. A first dielectric layer is formed on a substrate. A cap layer is formed on the first dielectric layer. A second dielectric layer is formed on the cap layer. A node contact hole is formed to penetrate through the second dielectric layer, the cap layer and the first dielectric layer. A liner layer is formed on a sidewall of the node contact hole. A restraining layer is formed on the second dielectric layer. A patterned conductive layer is formed on a portion of the restraining layer and fills the node contact hole. A selective hemispherical grained layer is formed on the patterned conductive layer.

摘要翻译： 一种制造电容器的底部电极的方法。 在基板上形成第一电介质层。 在第一电介质层上形成覆盖层。 在盖层上形成第二电介质层。 形成节点接触孔以穿透第二介电层，盖层和第一介电层。 衬垫层形成在节点接触孔的侧壁上。 在第二电介质层上形成限制层。 在限制层的一部分上形成有图案的导电层，并填充节点接触孔。 在图案化的导电层上形成选择性半球形纹理层。

公开(公告)号：US6150223A

公开(公告)日：2000-11-21

申请号：US287881

申请日：1999-04-07

申请人： Horng-Non Chern ,  Kun-Chi Lin ,  Alex Hou ,  Chien-Hua Tsai ,  Tsu-An Lin

发明人： Horng-Non Chern ,  Kun-Chi Lin ,  Alex Hou ,  Chien-Hua Tsai ,  Tsu-An Lin

IPC分类号： H01L21/60 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/76

CPC分类号： H01L21/76897 ,  H01L21/823468

摘要： A method for forming a different width of gate spacer is disclosed. The method includes firstly forming a gate oxide layer on a semiconductor substrate. A polysilicon layer, a conductive layer, a first dielectric layer are formed in order on the gate oxide layer. The first dielectric layer, the conductive layer, the polysilicon layer, and the gate oxide layer are further etched using them as the interior gate and the peripheral gate. Next, second dielectric layer, third dielectric layer, and fourth dielectric layer are formed over the interior gate and the peripheral gate, and a first photoresist layer abuts the surface of the fourth dielectric layer of the interior circuit. Moreover, etching the fourth dielectric layer of peripheral gate to form a second spacer of peripheral gate, and etching the third dielectric layer of the peripheral gate are undertaken to form a first spacer of the peripheral gate. Removing the first photoresist layer and the fourth dielectric layer of the interior circuit, a fifth dielectric layer is formed on the third dielectric layer of the interior circuit. The fourth dielectric layer and the top surface of the second dielectric layer of the peripheral circuit are removed. The fifth dielectric layer is formed on the first dielectric layer and the third peripheral of the peripheral circuit, and then the second photoresist layer on the fifth dielectric layer, wherein the third photoresist layer is patterned as a bit-line contact via of the interior circuit and the bit-line contact vias of the peripheral circuit. Finally, anisotropically etching the third photoresist layer and the fifth dielectric layer, a bit-line to the substrate contact via and a bit-line to the gate contact via are formed inside the fifth dielectric layer.

摘要翻译： 公开了一种用于形成不同宽度的栅极间隔物的方法。 该方法包括首先在半导体衬底上形成栅氧化层。 在栅极氧化物层上依次形成多晶硅层，导电层，第一介电层。 使用它们作为内部栅极和外围栅极进一步蚀刻第一介电层，导电层，多晶硅层和栅极氧化物层。 接下来，在内部栅极和外围栅极上形成第二电介质层，第三电介质层和第四电介质层，并且第一光致抗蚀剂层邻接内部电路的第四电介质层的表面。 此外，蚀刻外围栅极的第四介电层以形成外围栅极的第二间隔物，并且蚀刻外围栅极的第三介电层以形成外围栅极的第一间隔物。 去除内部电路的第一光致抗蚀剂层和第四电介质层，在内部电路的第三电介质层上形成第五电介质层。 除去第四电介质层和外围电路的第二电介质层的顶表面。 第五电介质层形成在第一电介质层和外围电路的第三外围，然后形成在第五介电层上的第二光致抗蚀剂层，其中第三光致抗蚀剂层被图案化为内部电路的位线接触通孔 和外围电路的位线接触通孔。 最后，在第五介电层内形成各向异性蚀刻第三光致抗蚀剂层和第五电介质层，到基板接触通孔的位线和到栅极接触通孔的位线。

公开(公告)号：US06124161A

公开(公告)日：2000-09-26

申请号：US203022

申请日：1998-12-01

申请人： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

发明人： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8234

CPC分类号： H01L28/84 ,  H01L27/10852

摘要： A method for forming a hemispherical silicon grain (HSG) layer on a polysilicon electrode is provided. The method is suitable for a substrate, which has a dielectric layer over the substrate with an opening to expose the substrate, and a polysilicon layer is formed over the substrate. A portion of the polysilicon layer is removed above dielectric layer other than the opening region. Each sidewall of the polysilicon layer is slanted so that a trapezoidal polysilicon base is formed. A buffer layer is formed over the trapezoidal polysilicon base. An ion implantation process is performed to form an amorphous silicon layer with sufficient depth on a top surface region of the trapezoidal polysilicon base. The buffer layer includes silicon oxide or silicon nitride. During ion implantation, oxygen or nitrogen elements can also be bombarded into the amorphous silicon layer so as to buffer the amorphous silicon layer to be re-crystallized. A selective HSG layer is formed on the trapezoidal polysilicon electrode base.

摘要翻译： 提供了一种在多晶硅电极上形成半球形硅晶粒（HSG）层的方法。 该方法适合于在衬底上具有介电层的衬底，其具有用于暴露衬底的开口，并且在衬底上形成多晶硅层。 除了开口区域之外，在介电层上除去多晶硅层的一部分。 多晶硅层的每个侧壁都是倾斜的，从而形成梯形多晶硅基底。 缓冲层形成在梯形多晶硅基底上。 执行离子注入工艺以在梯形多晶硅基底的顶表面区域上形成具有足够深度的非晶硅层。 缓冲层包括氧化硅或氮化硅。 在离子注入期间，也可以将氧或氮元素轰击到非晶硅层中，以缓冲非晶硅层再结晶。 在梯形多晶硅电极基体上形成选择性HSG层。

公开(公告)号：US20100157627A1

公开(公告)日：2010-06-24

申请号：US12390309

申请日：2009-02-20

申请人： Kuan-Sheng Wang ,  Kun-Chi Lin ,  Ying-Chieh Wang ,  Shu-Hao Chang

发明人： Kuan-Sheng Wang ,  Kun-Chi Lin ,  Ying-Chieh Wang ,  Shu-Hao Chang

IPC分类号： H02M3/22 ,  G05F1/10 ,  G05F1/00

CPC分类号： G01R19/0084

摘要： An output voltage detecting circuit includes a conducting structure, a voltage regulator, a first resistor and a second resistor. The conducting structure includes a power output return terminal, a first contact and a second contact. A compensating voltage is generated between the first and second contacts when an output current flows through the first and second contacts. The voltage regulator adjusts a first current according to a voltage across a first circuit terminal and the ground terminal of the voltage regulator, thereby generating a detecting signal according to the first current. An output voltage across the positive power output terminal and the power output return terminal is subject to voltage division by the first and second resistors to generate a divided voltage. The voltage across the first circuit terminal and the ground terminal of the voltage regulator is equal to a difference between the divided voltage and the compensating voltage.

摘要翻译： 输出电压检测电路包括导电结构，电压调节器，第一电阻器和第二电阻器。 导电结构包括电源输出返回端子，第一触点和第二触点。 当输出电流流过第一和第二触点时，在第一和第二触点之间产生补偿电压。 电压调节器根据第一电路端子和电压调节器的接地端子之间的电压来调节第一电流，从而根据第一电流产生检测信号。 正功率输出端子和功率输出返回端子两端的输出电压经受第一和第二电阻器的分压以产生分压。 电压调节器的第一电路端子和接地端子之间的电压等于分压和补偿电压之间的差值。

公开(公告)号：US06479355B2

公开(公告)日：2002-11-12

申请号：US09784235

申请日：2001-02-13

申请人： King-Lung Wu ,  Kun-Chi Lin

发明人： King-Lung Wu ,  Kun-Chi Lin

IPC分类号： H01L21336

CPC分类号： H01L21/76895 ,  H01L21/823425 ,  H01L21/823475

摘要： The present invention provides a method for landing pads in the semiconductor devices, comprising the following steps: providing a semiconductor substrates with a plurality of active regions, a plurality of gate structures above the active regions and a plurality of source/drain regions, while each gate structure comprises a top cap layer and sidewall spacers; forming a conductive layer over the substrate; removing a portion of the conductive layer above the gate structure using the top cap layer of the gate structure as a stop layer, so that a height of the conductive layer is lower than a height of the gate structure; forming a patterned mask layer, right above the active regions, over the substrate; performing an etching step to define the conductive layer above the active regions; and removing the patterned mask layer and forming landing pads on the active regions.

摘要翻译： 本发明提供一种在半导体器件中着陆焊盘的方法，包括以下步骤：提供具有多个有源区域的半导体衬底，有源区域上方的多个栅极结构和多个源极/漏极区域，而每个 栅极结构包括顶盖层和侧壁间隔物; 在衬底上形成导电层; 使用栅极结构的顶盖层作为阻挡层去除栅极结构上方的导电层的一部分，使得导电层的高度低于栅极结构的高度; 在所述有源区上方形成图案化掩模层; 执行蚀刻步骤以限定所述有源区上方的所述导电层; 并去除图案化的掩模层并在活性区上形成着色焊盘。

公开(公告)号：US06297139B1

公开(公告)日：2001-10-02

申请号：US09479921

申请日：2000-01-10

申请人： Kun-Chi Lin

发明人： Kun-Chi Lin

IPC分类号： H01L2144

CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76816

摘要： The present invention provides a method of forming a contact hole of a DRAM on a semiconductor wafer. The semiconductor wafer comprises a substrate, a conductive layer positioned in a predetermined area of the substrate and a dielectric layer positioned on the surface of the substrate and covering the conductive layer. The method comprises forming an amorphous silicon ( &agr;-Si) layer with an opening on the surface of the dielectric layer wherein the opening is positioned directly above the conductive layer and penetrates to the surface of the dielectric layer, forming a polysilicon layer uniformly on the surface of the amorphous silicon layer and performing a dry etching process to form a contact hole in the dielectric layer, the amorphous silicon layer and the polysilicon layer being used as a hard mask, the contact hole penetrating through the dielectric layer down to the surface of the conductive layer. The polysilicon layer is formed by performing a hemi-spherical grain (HSG) process to improve the resolution limit of the optical exposure tool of the lithographic process.

摘要翻译： 本发明提供一种在半导体晶片上形成DRAM的接触孔的方法。 半导体晶片包括衬底，位于衬底的预定区域中的导电层和位于衬底的表面上并覆盖导电层的电介质层。 该方法包括在电介质层的表面上形成具有开口的非晶硅（α-Si）层，其中开口位于导电层的正上方，并穿透到电介质层的表面，在 并且进行干蚀刻工艺以在介电层中形成接触孔，非晶硅层和多晶硅层用作硬掩模，该接触孔穿过电介质层向下延伸到 导电层。 通过执行半球形晶粒（HSG）工艺来形成多晶硅层，以提高光刻工艺的光学曝光工具的分辨率极限。

公开(公告)号：US06204107B1

公开(公告)日：2001-03-20

申请号：US09208611

申请日：1998-12-08

申请人： Kuo-Chi Lin ,  Kuen-Yow Lin ,  Chien-Hua Tsai ,  Kun-Chi Lin

发明人： Kuo-Chi Lin ,  Kuen-Yow Lin ,  Chien-Hua Tsai ,  Kun-Chi Lin

IPC分类号： H01L218234

CPC分类号： H01L21/76831 ,  H01L21/76832

摘要： A method for forming a multi-layered liner on the sidewalls of a node contact opening includes the steps of providing a substrate having a dielectric layer thereon. The dielectric layer further includes a node contact opening that exposes a portion of the substrate. A first liner layer is then formed on the sidewalls of the node contact opening. Next, a second liner layer is formed over the first liner layer such that the first liner layer and the second liner layer together form a dual-layered liner. The first liner layer in contact with the dielectric layer has good insulation capacity while the second liner layer has good etch-resisting property.

摘要翻译： 在节点接触开口的侧壁上形成多层衬垫的方法包括以下步骤：提供其上具有介电层的衬底。 电介质层还包括暴露基板的一部分的节点接触开口。 然后在节点接触开口的侧壁上形成第一衬垫层。 接下来，在第一衬里层上形成第二衬里层，使得第一衬里层和第二衬里层一起形成双层衬垫。 与电介质层接触的第一衬垫层具有良好的绝缘能力，而第二衬垫层具有良好的抗蚀性能。

公开(公告)号：US6150216A

公开(公告)日：2000-11-21

申请号：US222737

申请日：1998-12-29

申请人： Kuo-Chi Lin ,  Kun-Chi Lin

发明人： Kuo-Chi Lin ,  Kun-Chi Lin

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/20 ,  H01G4/06 ,  H01G4/30

CPC分类号： H01L28/84 ,  H01L21/76895 ,  H01L27/10855 ,  H01L28/60

摘要： A method for forming an electrode of semiconductor device capacitor is disclosed. The method comprises forming a dielectric layer on a semiconductor substrate and then using photolithographic method to etch a trench through the dielectric layer to expose specific part of the semiconductor substrate. A polysilicon layer is then formed over the dielectric layer and filled the trench. The polysilicon layer is patterned by a photoresist layer and etched back to the dielectric layer, then a polysilicon rod is formed. A spacer method is used to form an amorphized silicon spacer is sidewall of the polysilicon rod. The polysilicon rod is then implanted to form an amorphized polysilicon layer on top surface of the polysilicon rod. Final hemispherical grain silicon is formed on the spacer and the amorphized polysilicon layer to increase the surface area of the polysilicon rod. Thereby, an electrode of a semiconductor device capacitor is formed, and the capacitance of capacitor is enhanced.

摘要翻译： 公开了一种形成半导体器件电容器的电极的方法。 该方法包括在半导体衬底上形成电介质层，然后使用光刻法蚀刻通过电介质层的沟槽，以露出半导体衬底的特定部分。 然后在电介质层上形成多晶硅层，并填充沟槽。 通过光致抗蚀剂层将多晶硅层图案化并回蚀刻到电介质层，然后形成多晶硅棒。 使用间隔法形成非晶硅衬垫是多晶硅棒的侧壁。 然后植入多晶硅棒以在多晶硅棒的顶表面上形成非晶化多晶硅层。 在间隔物和非晶化多晶硅层上形成最终的半球形晶粒硅以增加多晶硅棒的表面积。 由此，形成半导体器件电容器的电极，提高电容器的电容。

公开(公告)号：US06667234B2

公开(公告)日：2003-12-23

申请号：US09789358

申请日：2001-02-20

申请人： King-Lung Wu ,  Tzung-Han Lee ,  Kun-Chi Lin

发明人： King-Lung Wu ,  Tzung-Han Lee ,  Kun-Chi Lin

IPC分类号： H01L2144

CPC分类号： H01L21/76802

摘要： A method of fabricating a node contact on a substrate, which contains a first conductive device and an insulating layer covering the substrate and the first conductive device, includes forming at least two conductive lines on the insulating layer, wherein the conductive lines are separated by a first distance; forming at least two second conductive devices on the insulating layer, wherein the second conductive devices are separated by a second distance, and wherein one of the conductive lines and one of the second conductive devices are separated by a third distance, and wherein both the first and second distances are greater than the third distance; forming an isolation layer of a thickness on the substrate to cover the insulating layer, the conductive lines and the second conductive devices, wherein the isolation layer comprises a dished area located between the second conductive devices; removing a portion of the isolation layer to form a spacer around the second conductive devices, and to deepen the dished area to form an opening exposing the insulating layer; deepening the opening to expose the first conductive device; and filling the opening with a conductive material.