公开(公告)号：US20080237685A1

公开(公告)日：2008-10-02

申请号：US11822548

申请日：2007-07-06

申请人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

发明人： Byung-Kyu Cho ,  Se-Hoon Lee ,  Kyu-Charn Park ,  Choong-Ho Lee

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： In one embodiment, the semiconductor memory device includes a semiconductor substrate having projecting portions, a tunnel insulation layer formed over at least one of the projecting semiconductor substrate portions, and a floating gate structure disposed over the tunnel insulation layer. An upper portion of the floating gate structure is wider than a lower portion of the floating gate structure, and the lower portion of the floating gate structure has a width less than a width of the tunnel insulating layer. First insulation layer portions are formed in the semiconductor substrate and project from the semiconductor substrate such that the floating gate structure is disposed between the projecting first insulation layer portions. A dielectric layer is formed over the first insulation layer portions and the floating gate structure, and a control gate is formed over the dielectric layer.

摘要翻译： 在一个实施例中，半导体存储器件包括具有突出部分的半导体衬底，在至少一个突出半导体衬底部分上形成的隧道绝缘层，以及设置在隧道绝缘层上的浮动栅极结构。 浮动栅极结构的上部比浮动栅极结构的下部宽，并且浮动栅极结构的下部具有小于隧道绝缘层的宽度的宽度。 第一绝缘层部分形成在半导体衬底中并从半导体衬底突出，使得浮栅结构设置在突出的第一绝缘层部分之间。 在第一绝缘层部分和浮动栅极结构之上形成电介质层，并且在电介质层上形成控制栅极。

公开(公告)号：US06979628B2

公开(公告)日：2005-12-27

申请号：US10726788

申请日：2003-12-02

申请人： Hong-Soo Kim ,  Kyu-Charn Park ,  Jung-Dal Choi ,  Seong-Soon Cho

发明人： Hong-Soo Kim ,  Kyu-Charn Park ,  Jung-Dal Choi ,  Seong-Soon Cho

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/76205 ,  H01L21/76213 ,  H01L21/76232 ,  H01L21/76237

摘要： Semiconductor devices and methods of forming devices that have field oxides in trenches are disclosed. According to the methods, a semiconductor substrate is prepared. An upper trench is formed at a predetermined region of the semiconductor substrate and a bottom trench is formed at a bottom surface of the upper trench. A field oxide is formed to fill the bottom trench and the upper trench. At this time, the upper trench has a wider width than the bottom trench.

摘要翻译： 公开了在沟槽中形成具有场氧化物的器件的半导体器件和方法。 根据该方法制备半导体衬底。 在半导体衬底的预定区域处形成上沟槽，并且在上沟槽的底表面处形成底沟槽。 形成场氧化物以填充底部沟槽和上部沟槽。 此时，上沟槽的宽度比底沟宽。

公开(公告)号：US08120091B2

公开(公告)日：2012-02-21

申请号：US12128078

申请日：2008-05-28

申请人： Suk-Kang Sung ,  Choong-Ho Lee ,  Sang-wook Lim ,  Dong-Uk Choi ,  Hee-Soo Kang ,  Kyu-Charn Park

发明人： Suk-Kang Sung ,  Choong-Ho Lee ,  Sang-wook Lim ,  Dong-Uk Choi ,  Hee-Soo Kang ,  Kyu-Charn Park

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction.

摘要翻译： 非易失性存储器件包括衬底和隧道绝缘层图案，使得隧道绝缘图案的每个部分沿着第一方向延伸，并且隧道绝缘层图案的相邻部分可以在基本垂直的第二方向上分离 到第一个方向。 非易失性存储器件可以包括形成在隧道绝缘层图案上的栅极结构。 栅极结构可以包括沿着第二方向形成在隧道绝缘层图案上的浮动栅极，在第二方向上形成在浮置栅极上的第一导电层图案，沿着第二方向形成在第一导电层图案上的电介质层图案 以及在第二方向上形成在电介质层图案上的控制栅极。

公开(公告)号：US07615437B2

公开(公告)日：2009-11-10

申请号：US12153071

申请日：2008-05-13

申请人： Suk-Kang Sung ,  Kyu-Charn Park ,  Choong-Ho Lee

发明人： Suk-Kang Sung ,  Kyu-Charn Park ,  Choong-Ho Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/743 ,  H01L21/28123 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A method of manufacturing a non-volatile memory device includes sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on a substrate, forming a first opening through the resultant structure to expose the substrate, forming second and third openings through the second insulation layer to form a second insulation layer pattern, forming a conductive layer on the second insulation layer pattern, forming a photoresist pattern structure on the conductive layer, and forming simultaneously a common source line, at least one ground selection line, at least one string selection line, and a plurality of gate structures on the substrate by etching through the photoresist pattern structure, wherein the common source line and the gate structures are formed simultaneously on a substantially same level and of substantially same components.

摘要翻译： 一种制造非易失性存储器件的方法包括在衬底上依次沉积第一绝缘层，电荷存储层和第二绝缘层，形成通过所得结构的第一开口以露出衬底，形成第二和第三开口 通过第二绝缘层形成第二绝缘层图案，在第二绝缘层图案上形成导电层，在导电层上形成光致抗蚀剂图形结构，同时形成共同的源极线，至少一个接地选择线， 至少一个串选择线，以及通过蚀刻通过光致抗蚀剂图案结构在衬底上的多个栅极结构，其中公共源极线和栅极结构同时形成在基本相同的水平面上并且基本上相同的部件。

公开(公告)号：US07602633B2

公开(公告)日：2009-10-13

申请号：US11946737

申请日：2007-11-28

申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

IPC分类号： G11C11/00

CPC分类号： H01L29/685

摘要： A non-volatile memory device includes a substrate, resistance patterns, a gate dielectric layer, a gate electrode pattern, a first impurity region and a second impurity region. The substrate has recesses. The recesses are filled with the resistance patterns. The resistance patterns include a material having a resistance that is variable in accordance with a voltage applied thereto. The gate dielectric layer is formed on the substrate. The gate electrode pattern is formed on the gate dielectric layer. The first and second impurity regions are formed in the substrate. The first impurity region and the second impurity region contact side surfaces of the resistance patterns. Further, the resistance patterns, the first impurity region and the second impurity region define a channel region. Thus, the non-volatile memory device may store data using a variable resistance of the resistance patterns so that the non-volatile memory device may have excellent operational characteristics.

摘要翻译： 非易失性存储器件包括衬底，电阻图案，栅极介电层，栅极电极图案，第一杂质区域和第二杂质区域。 基板有凹槽。 凹槽中填充有电阻图案。 电阻图案包括具有根据施加到其上的电压而可变的电阻的材料。 栅极电介质层形成在基板上。 栅极电极图案形成在栅极介电层上。 在衬底中形成第一和第二杂质区。 电阻图案的第一杂质区和第二杂质区接触侧表面。 此外，电阻图案，第一杂质区域和第二杂质区域限定沟道区域。 因此，非易失性存储器件可以使用电阻图案的可变电阻来存储数据，使得非易失性存储器件可以具有优异的操作特性。

公开(公告)号：US20050088889A1

公开(公告)日：2005-04-28

申请号：US10975933

申请日：2004-10-28

申请人： Chang-Hyun Lee ,  Kyu-Charn Park

发明人： Chang-Hyun Lee ,  Kyu-Charn Park

IPC分类号： G11C7/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

摘要翻译： 非易失性存储器件包括具有第一区域和第二区域的衬底。 第一栅电极设置在第一区域上。 在第一栅电极和基板之间插入多层电荷存储层，多层电荷存储包括依次堆叠的隧道绝缘，阱绝缘和阻挡绝缘层。 第二栅极被放置在第二区域的衬底上，第二栅极包括下栅极和连接到下栅极的上表面区域的上栅极。 栅极绝缘层介于第二栅电极和衬底之间。 第二栅电极的第一栅电极和上栅极包括相同的材料。

公开(公告)号：US4828875A

公开(公告)日：1989-05-09

申请号：US170326

申请日：1988-03-18

申请人： Ho-Bin Im ,  Kyu-Charn Park

发明人： Ho-Bin Im ,  Kyu-Charn Park

IPC分类号： H01M8/00 ,  C03C17/22 ,  H01L31/0296 ,  H01L31/18

CPC分类号： H01L31/1832 ,  C03C17/22 ,  H01L31/02966 ,  C03C2217/288 ,  C03C2218/17 ,  C03C2218/32

摘要： Sintered films of Cd.sub.1-x Zn.sub.x S (0.ltoreq.x

摘要翻译： 提供了具有高透光率的Cd1-xZnxS（0

公开(公告)号：US07534684B2

公开(公告)日：2009-05-19

申请号：US11799685

申请日：2007-05-02

申请人： Chang-Hyun Lee ,  Kyu-Charn Park

发明人： Chang-Hyun Lee ,  Kyu-Charn Park

IPC分类号： H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

摘要翻译： 非易失性存储器件包括具有第一区域和第二区域的衬底。 第一栅电极设置在第一区域上。 在第一栅电极和基板之间插入多层电荷存储层，多层电荷存储包括依次堆叠的隧道绝缘，阱绝缘和阻挡绝缘层。 第二栅极被放置在第二区域的衬底上，第二栅极包括下栅极和连接到下栅极的上表面区域的上栅极。 栅极绝缘层介于第二栅电极和衬底之间。 第二栅电极的第一栅电极和上栅极包括相同的材料。

公开(公告)号：US20080296657A1

公开(公告)日：2008-12-04

申请号：US12128078

申请日：2008-05-28

申请人： Suk-Kang Sung ,  Choong-Ho Lee ,  Sang-wook Lim ,  Dong-Uk Choi ,  Hee-Soo Kang ,  Kyu-Charn Park

发明人： Suk-Kang Sung ,  Choong-Ho Lee ,  Sang-wook Lim ,  Dong-Uk Choi ,  Hee-Soo Kang ,  Kyu-Charn Park

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A non-volatile memory device includes a substrate and a tunnel insulation layer pattern, such that each portion of the tunnel insulation pattern extends along a first direction and adjacent portions of the tunnel insulation layer pattern may be separated in a second direction that is substantially perpendicular to the first direction. A non-volatile memory device may include a gate structure formed on the tunnel insulation layer pattern. The gate structure may include a floating gate formed on the tunnel insulation layer pattern along the second direction, a first conductive layer pattern formed on the floating gate in the second direction, a dielectric layer pattern formed on the first conductive layer pattern along the second direction, and a control gate formed on the dielectric layer pattern in the second direction.

摘要翻译： 非易失性存储器件包括衬底和隧道绝缘层图案，使得隧道绝缘图案的每个部分沿着第一方向延伸，并且隧道绝缘层图案的相邻部分可以在基本垂直的第二方向上分离 到第一个方向。 非易失性存储器件可以包括形成在隧道绝缘层图案上的栅极结构。 栅极结构可以包括沿着第二方向形成在隧道绝缘层图案上的浮动栅极，在第二方向上形成在浮置栅极上的第一导电层图案，沿着第二方向形成在第一导电层图案上的电介质层图案 以及在第二方向上形成在电介质层图案上的控制栅极。

公开(公告)号：US20080001209A1

公开(公告)日：2008-01-03

申请号：US11783548

申请日：2007-04-10

申请人： Eun-Suk Cho ,  Kyu-Charn Park ,  Jong-Jin Lee ,  Jeong-Dong Choe

发明人： Eun-Suk Cho ,  Kyu-Charn Park ,  Jong-Jin Lee ,  Jeong-Dong Choe

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336

摘要： A non-volatile memory device may include a substrate having a field region and an active region including a rounded upper edge portion and a flat upper central portion, an effective tunnel oxide layer on the flat upper central portion of the active region, a split floating gate electrode on the effective tunnel oxide layer, the floating gate electrode having a width greater than a width of the effective tunnel oxide layer, a dielectric layer pattern on the floating gate electrode, the dielectric layer pattern including metal oxide, and a control gate electrode on the dielectric layer pattern.

摘要翻译： 非易失性存储器件可以包括具有场区域和包括圆形上边缘部分和平坦上中心部分的有源区域的基板，在有源区域的平坦上中心部分上的有效隧道氧化物层，分裂浮动 栅极电极在有效隧道氧化物层上，浮栅电极的宽度大于有效隧道氧化物层的宽度，浮栅电极上的电介质层图案，包括金属氧化物的电介质层图案和控制栅电极 在电介质层图案上。