公开(公告)号：US20130145238A1

公开(公告)日：2013-06-06

申请号：US13755676

申请日：2013-01-31

Applicant: LSI Corporation

Inventor： Abdel Hakim S. Alhussien ,  Erich F. Haratsch ,  Zongwang Li ,  Fan Zhang

IPC: H03M13/23

CPC classification number: H03M13/23 ,  G06F11/1072 ,  H03M13/1154 ,  H03M13/6325

Abstract: Methods and apparatus are provided for encoding and decoding in flash memories using convolutional-type low parity density check codes. A plurality of bits to be stored on a flash memory device are encoded using a convolutional-type low density parity check code, such as a spatially coupled low density parity check code. The encoded pages or portions thereof can be decoded independently of other pages. In one embodiment, an encoded page is decoded jointly with one or more additional pages in the same wordline or a different wordline.

Abstract translation: 提供了使用卷积型低奇偶校验密码校验码来对闪速存储器进行编码和解码的方法和装置。 使用诸如空间耦合的低密度奇偶校验码的卷积型低密度奇偶校验码对要存储在闪速存储器件上的多个比特进行编码。 编码的页面或其部分可以独立于其他页面被解码。 在一个实施例中，编码页面与同一字线或不同字线中的一个或多个附加页面联合解码。

公开(公告)号：US20130145235A1

公开(公告)日：2013-06-06

申请号：US13755717

申请日：2013-01-31

Applicant: LSI Corporation

Inventor： Abdel Hakim S. Alhussien ,  Zongwang Li ,  Erich F. Haratsch ,  Ludovic Danjean

IPC: G06F11/10

CPC classification number: G06F11/1008 ,  G06F11/1048 ,  G11C8/12 ,  G11C11/5621

Abstract: Methods and apparatus are provided for detection and decoding in flash memories with selective binary and non-binary decoding. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting; the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and jointly decoding the plurality of bits using the non-binary log likelihood ratio, wherein the pages are encoded independently.

Abstract translation: 提供了用于具有选择性二进制和非二进制解码的闪存中的检测和解码的方法和装置。 来自闪存设备的数据通过从闪存设备的一个或多个页面获得多个位的一个或多个读取值来处理; 转换 基于当从多个比特读取特定模式时将给定数据模式写入多个比特的概率，将所述多个比特的一个或多个读取值提高为非二进制对数似然比; 并使用非二进制对数似然比联合解码多个比特，其中页面被独立编码。

公开(公告)号：US09037952B2

公开(公告)日：2015-05-19

申请号：US13760609

申请日：2013-02-06

Applicant: LSI Corporation

Inventor： Zongwang Li ,  Yang Han ,  Kaichi Zhang ,  Chung-Li Wang

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/27

CPC classification number: G06F11/10 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/2707 ,  H03M13/6505 ,  H03M13/6566

Abstract: A hard decision memory interacts with a multi-layered low-density parity-check decoder by sending multiple L values and E values to a multi-layered low-density parity-check decoder (LDPC), and the L value E value hard decision memory (LE hard decision memory) receives one or more hard decisions. The LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements. The use of the LE hard decision memory results improved multi-level LDPC decoding of an LDPC encoded message.

Abstract translation: 硬判决存储器通过向多层低密度奇偶校验解码器（LDPC）发送多个L值和E值与多层低密度奇偶校验解码器相互作用，并且L值E值硬判决存储器 （LE硬决策存储器）接收一个或多个硬判决。 LE硬判决存储器包括全局映射元件，用于交织来自第一和第二循环的L值，并将交织的值存储在第一存储器元件中。 然后，低密度奇偶校验解码器处理来自第一存储器元件的循环并将输出存储在第二存储元件中。 LE硬决策存储器不包括任何多路复用单元。 LE硬判决存储器的使用结果改进了LDPC编码消息的多级LDPC解码。

公开(公告)号：US08930792B2

公开(公告)日：2015-01-06

申请号：US13766891

申请日：2013-02-14

Applicant: LSI Corporation

Inventor： Shu Li ,  Shaohua Yang ,  Zongwang Li ,  Yang Han

IPC: H03M13/00 ,  H03M13/13 ,  H03M13/29 ,  G11B20/18 ,  H04L1/00

CPC classification number: H03M13/13 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1117 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/2978 ,  H03M13/6325 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. In some cases the systems include a low density parity check data decoder circuit including at least a first data decoder engine and a second data decoder engine each electrically coupled to a common circuit. The common circuit is operable to: shift a combination of both a first sub-message from the first data decoder engine and the second sub-message from the second data decoder engine to yield an shifted output, and disaggregate the shifted output to yield a third sub-message to the first data decoder engine and a fourth sub-message to the second decoder engine.

Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于利用多个数据流进行数据从存储设备的数据恢复的系统和方法。 在一些情况下，系统包括低密度奇偶校验数据解码器电路，其包括至少第一数据解码器引擎和第二数据解码器引擎，每个电耦合到公共电路。 公共电路可操作用于：将来自第一数据解码器引擎的第一子消息和来自第二数据解码器引擎的第二子消息的组合移位以产生移位的输出，并且分解转移的输出以产生第三 子消息发送到第一数据解码器引擎，第四子消息发送到第二解码器引擎。

公开(公告)号：US20140229806A1

公开(公告)日：2014-08-14

申请号：US13766891

申请日：2013-02-14

Applicant: LSI CORPORATION

Inventor： Shu Li ,  Shaohua Yang ,  Zongwang Li ,  Yang Han

IPC: H03M13/13 ,  G11B20/18

CPC classification number: H03M13/13 ,  G11B20/1833 ,  G11B2020/185 ,  H03M13/1117 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/2957 ,  H03M13/2975 ,  H03M13/2978 ,  H03M13/6325 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0052 ,  H04L1/0066

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing data decoding.

Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于执行数据解码的系统和方法。

公开(公告)号：US20140130061A1

公开(公告)日：2014-05-08

申请号：US13667450

申请日：2012-11-02

Applicant: LSI CORPORATION

Inventor： Zongwang Li ,  Chung-Li Wang ,  Kaitlyn T. Nguyen ,  Keklik Bayam Alptekin

IPC: G06F9/54

CPC classification number: G06F9/30145 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/616 ,  H03M13/6566

Abstract: The disclosure is directed to a system and method for storing and processing check-node unit (CNU) messages utilizing random access memory (RAM). A decoder includes a layered array of CNUs configured to receive at least one variable-node unit (VNU) message associated with decoded bits of at least one data segment being operated upon by the decoder. The decoder further includes a CNU message converter configured to permutate at least one initial circulant of the VNU message to generate a converted CNU message having sub-circulants sized for RAM-based processing. The decoder further includes RAM configured to store sub-circulants of the converted CNU message at addressable memory blocks for parallel VNU processing.

Abstract translation: 本公开涉及一种利用随机存取存储器（RAM）存储和处理校验节点单元（CNU）消息的系统和方法。 解码器包括CNU的分层阵列，其被配置为接收与解码器正在操作的至少一个数据段的解码比特相关联的至少一个可变节点单元（VNU）消息。 解码器还包括CNU消息转换器，其被配置为置换VNU消息的至少一个初始循环，以生成具有基于RAM的处理的子循环的转换的CNU消息。 解码器还包括RAM，其被配置为将转换的CNU消息的子循环存储在可寻址存储器块处以用于并行VNU处理。

公开(公告)号：US20140122971A1

公开(公告)日：2014-05-01

申请号：US13663006

申请日：2012-10-29

Applicant: LSI CORPORATION

Inventor： Zongwang Li ,  Lei Chen ,  Shaohua Yang ,  Johnson Yen

IPC: H03M13/13 ,  H03M13/27

CPC classification number: H03M13/6505 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/27 ,  H03M13/6331

Abstract: A memory in a LDPC decoding system includes data banks organized into a ping-pong memory. The ping-pong memory is connected to an interleaver and a de-interleaver. The interleaver interleaves L values; the interleaved L values are then stored in the ping-pong memory. A LDPC decoder retrieves L values from the ping-pong memory and returns E values to the ping-pong memory. The de-interleaver de-interleaves the E values and sends data to a LE queue and HD queue.

Abstract translation: LDPC解码系统中的存储器包括组织成乒乓存储器的数据库。 乒乓存储器连接到交织器和解交织器。 交织器交织L值; 然后将交错的L值存储在乒乓存储器中。 LDPC解码器从乒乓存储器检索L值并将E值返回给乒乓存储器。 解交织器对E值进行解交织，并将数据发送到LE队列和HD队列。

公开(公告)号：US20140089757A1

公开(公告)日：2014-03-27

申请号：US13624927

申请日：2012-09-22

Applicant: LSI CORPORATION

Inventor： Shaohua Yang ,  Chung-Li Wang ,  Dan Liu ,  Zongwang Li

IPC: H03M13/13

CPC classification number: H03M13/13 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1171 ,  H03M13/2957 ,  H03M13/6331 ,  H03M13/658

Abstract: The present inventions are related to systems and methods for an LDPC decoder with fractional local iterations that may be used in a data processing system with an LDPC decoder and data detector to better balance processing times in the LDPC decoder and data detector.

Abstract translation: 本发明涉及具有分数局部迭代的LDPC解码器的系统和方法，其可以在具有LDPC解码器和数据检测器的数据处理系统中使用以更好地平衡LDPC解码器和数据检测器中的处理时间。

公开(公告)号：US09048874B2

公开(公告)日：2015-06-02

申请号：US13886103

申请日：2013-05-02

Applicant: LSI Corporation

Inventor： Chung-Li Wang ,  Zongwang Li ,  Shu Li ,  Fan Zhang ,  Shaohua Yang

IPC: H03M13/00 ,  H03M13/13 ,  H03M13/11

CPC classification number: H03M13/13 ,  H03M13/1122 ,  H03M13/1125 ,  H03M13/1171 ,  H03M13/6583

Abstract: An apparatus for decoding data includes a variable node processor, a check node processor, and a field transformation circuit. The variable node processor is operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages. The check node processor is operable to generate the check node to variable node messages and to calculate checksums based on variable node to check node messages. The variable node processor and the check node processor comprise different Galois fields. The field transformation circuit is operable to transform the variable node to check node messages from a first of the different Galois fields to a second of the Galois fields.

Abstract translation: 用于解码数据的装置包括可变节点处理器，校验节点处理器和场变换电路。 可变节点处理器可操作以生成变量节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知值。 校验节点处理器可用于将校验节点生成到可变节点消息，并且基于变量节点来计算校验和以检查节点消息。 可变节点处理器和校验节点处理器包括不同的伽罗瓦域。 场变换电路可操作以将变量节点变换为将来自不同伽罗瓦域中的第一个的节点消息校验到伽罗瓦域中的第二个。

公开(公告)号：US09048867B2

公开(公告)日：2015-06-02

申请号：US13898685

申请日：2013-05-21

Applicant: LSI Corporation

Inventor： Dan Liu ,  Qi Zuo ,  Chung-Li Wang ,  Zongwang Li ,  Lei Wang

IPC: H03M13/11 ,  H04L1/00

CPC classification number: H03M13/1105 ,  H03M13/1114 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1131 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/1174 ,  H03M13/6331 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583 ,  H04L1/005

Abstract: An apparatus for layered low density parity check decoding includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node messages and to calculate perceived data values based on check node to variable node messages. The check node processor includes an intermediate message generator circuit operable to generate intermediate check node messages, a shift register based memory operable to store the intermediate check node messages, and at least one check node to variable node message generator circuit operable to generate the check node to variable node messages based on the intermediate check node messages from the shift register based memory.

Abstract translation: 用于分层低密度奇偶校验解码的装置包括可变节点处理器和校验节点处理器。 可变节点处理器可操作以生成可变节点以检查节点消息，并且基于校验节点到可变节点消息来计算感知数据值。 校验节点处理器包括可操作以产生中间校验节点消息的中间消息发生器电路，可操作以存储中间校验节点消息的移位寄存器的存储器，以及至少一个校验节点，可变节点消息生成器电路可操作以生成校验节点 基于来自基于移位寄存器的存储器的中间检查节点消息到可变节点消息。