公开(公告)号：US6141456A

公开(公告)日：2000-10-31

申请号：US1700

申请日：1997-12-31

申请人： Larry Pearlstein ,  Sharif M. Sazzad

发明人： Larry Pearlstein ,  Sharif M. Sazzad

IPC分类号： H04N7/30 ,  G06T3/40 ,  G06T9/00 ,  H04N1/387 ,  H04N7/26 ,  H04N7/46 ,  H04N7/50 ,  G06K9/36 ,  G06K9/32 ,  G06K9/46

CPC分类号： G06T3/4084 ,  H04N19/126 ,  H04N19/48 ,  H04N19/59 ,  H04N19/61 ,  H04N19/90

摘要： Methods and apparatus for combining linear image post-processing operations with an inverse discrete cosine transform (IDCT) operation are described. In accordance with various embodiments of the present invention IDCT and downsampling operations are combined into a single operation to achieve the same image processing result as sequential IDCT and downsampling operations. By combining the two operations and performing downsampling in the DCT, as opposed to pixel domain, significant complexity reduction is achieved over embodiments where the two operations are performed sequentially. In one particular embodiment, when interlaced images are being processed, combined IDCT/downsampling circuits which perform field based, as opposed to frame based, downsampling in the DCT domain are employed. The method and apparatus of the present invention can be used to implement circuits which perform a combined full order IDCT/downsampling operation and/or a reduced complexity combined full order IDCT/downsampling operation. The combined IDCT/downsampling methods and apparatus of the present invention are capable of supporting a wide range of downsampling ratios using, at least in some cases, fewer math operators, than are required to implement zonal filtering followed by a reduced order IDCT operation which requires the use of a contiguous subblock of DCT coefficients.

摘要翻译： 描述了将线性图像后处理操作与逆离散余弦变换（IDCT）操作组合的方法和装置。 根据本发明的各种实施例，IDCT和下采样操作被组合成单个操作以实现与顺序IDCT和下采样操作相同的图像处理结果。 通过组合这两个操作并在DCT中执行下采样，与像素域相反，实现了在顺序执行两个操作的实施例中显着的复杂度降低。 在一个特定实施例中，当正在处理隔行扫描图像时，采用在DCT域中执行基于场的组合IDCT /下采样电路，而不是基于帧的下采样。 本发明的方法和装置可用于实现执行组合的全序IDCT /下采样操作和/或降低复杂度的组合式全序列IDCT /下采样操作的电路。 本发明的组合的IDCT /下采样方法和装置能够使用至少在一些情况下使用较少的数学运算符来支持大范围的下采样比率，而不是实现区域过滤，然后是减少订单IDCT操作所需的，这需要 使用DCT系数的连续子块。

公开(公告)号：US6061400A

公开(公告)日：2000-05-09

申请号：US974907

申请日：1997-11-20

申请人： Larry Pearlstein ,  John Henderson ,  Jack Fuhrer

发明人： Larry Pearlstein ,  John Henderson ,  Jack Fuhrer

IPC分类号： H04N11/04 ,  G06T9/00 ,  H04N1/41 ,  H04N7/26 ,  H04N7/36 ,  H04N7/46 ,  H04N1/66 ,  H04N7/12

CPC分类号： H04N19/51 ,  H04N19/59

摘要： Techniques for identifying blocks of pixels, referred to as constant block regions, having approximately the same intensity in terms of luminance values, are discussed. High contrast vertical and/or horizontal edges will cause significant prediction errors in images generated by reduced resolution decoders under certain conditions. Methods for assessing when such conditions exist and a significant prediction error is likely to occur are described. In addition methods and apparatus for minimizing the effect of such prediction errors in downsampling decoders are also described. One specific embodiment is directed to a new video decoder which decodes portions of a single image, e.g., frame, at different resolutions. Areas of the image along high contrast vertical or horizontal edges are decoded at full resolution while other portions of the same image are decoded at reduced resolution. By decoding and storing portions of reduced resolution images at full resolution for reference purposes, the risk of prediction errors resulting from the use of downsampling on reference frames is reduced.

摘要翻译： 讨论了用于识别在亮度值方面具有近似相同强度的被称为恒定块区域的像素块的技术。 高对比度垂直和/或水平边缘将在特定条件下由降低分辨率解码器产生的图像中产生显着的预测误差。 描述了何时存在这种条件以及可能发生显着的预测误差的方法。 此外，还描述了用于最小化下采样解码器中的这种预测误差的影响的方法和装置。 一个具体实施例涉及一种以不同分辨率解码单个图像（例如，帧）的部分的新的视频解码器。 沿着高对比度的垂直或水平边缘的图像区域以全分辨率被解码，同时以降低的分辨率对相同图像的其他部分进行解码。 通过以全分辨率解码和存储分辨率降低的图像的部分用于参考目的，降低了在参考帧上使用下采样导致的预测误差的风险。

公开(公告)号：US5974185A

公开(公告)日：1999-10-26

申请号：US100632

申请日：1998-06-19

申请人： Jill Boyce ,  Larry Pearlstein

发明人： Jill Boyce ,  Larry Pearlstein

IPC分类号： G06T9/00 ,  H04N7/46 ,  H04N7/50 ,  G06K9/36

CPC分类号： H04N19/59 ,  H04N19/61

摘要： Plurality of encoding methods and apparatus for encoding video data in a manner that makes it well suited for decoding by either regular or downconverting decoders are described. In one embodiment, the selection and/or generation of motion vectors by an encoder is controlled so that only motion vectors having a size that corresponds to an integer multiple of a downsampling rate expected to be used by a downconverting decoder are generated and/or selected. In another embodiment, motion vectors having a size which corresponds to an integer multiple of an expected downsampling rate are preferred over other motion vectors. In various additional encoder embodiments feedback circuitry which models a downconverting decoder, and/or which provides feedback information on downconverted images generated by decoding the compressed video data generated by the encoder using a downconverting decoder, are incorporated into the encoder of the present invention.

摘要翻译： 描述了以通过正常或下变频解码器进行解码的方式对视频数据进行编码的多种编码方法和装置。 在一个实施例中，由编码器选择和/或产生运动矢量被控制，使得仅仅生成和/或选择具有对应于预期由下变频解码器使用的下采样率的整数倍的大小的运动矢量 。 在另一实施例中，具有对应于预期下采样率的整数倍的大小的运动矢量优于其它运动矢量。 在各种附加的编码器实施例中，对下变频解码器进行建模的反馈电路和/或提供关于通过使用下变频解码器解码由编码器产生的压缩视频数据而产生的下变频图像的反馈信息被并入本发明的编码器中。

公开(公告)号：US5828421A

公开(公告)日：1998-10-27

申请号：US468147

申请日：1995-06-06

申请人： Jill MacDonald Boyce ,  Larry Pearlstein ,  Frank Anton Lane

发明人： Jill MacDonald Boyce ,  Larry Pearlstein ,  Frank Anton Lane

IPC分类号： G06T3/40 ,  G06T9/00 ,  H04N5/44 ,  H04N5/445 ,  H04N5/45 ,  H04N5/46 ,  H04N7/24 ,  H04N7/26 ,  H04N7/36 ,  H04N7/46 ,  H04N7/50 ,  H04N21/431 ,  H04N21/4402

CPC分类号： H04N5/45 ,  G06T3/4084 ,  H04N19/122 ,  H04N19/132 ,  H04N19/159 ,  H04N19/162 ,  H04N19/172 ,  H04N19/176 ,  H04N19/18 ,  H04N19/184 ,  H04N19/40 ,  H04N19/42 ,  H04N19/423 ,  H04N19/427 ,  H04N19/428 ,  H04N19/44 ,  H04N19/48 ,  H04N19/59 ,  H04N19/61 ,  H04N21/4316 ,  H04N21/440254 ,  H04N5/4401 ,  H04N5/44504 ,  H04N5/44508 ,  H04N19/13 ,  H04N19/30 ,  H04N19/91 ,  H04N5/46

摘要： An implementation efficient video decoder suitable for use as a picture in picture decoder is described. In one embodiment, the video decoder receives primary and secondary bitstreams with the secondary bitstream including the video data intended to be displayed as inset pictures. The decoder uses many of the same circuit components on a time shared basis to decode both the main and inset pictures reducing the amount of circuitry required to implement the decoder. In one embodiment a preparser discards the majority of DCT coefficients in the secondary bitstream and the remaining data is variable length decoded and then variable length encoded using a non-MPEG compliant coding scheme prior to storing the inset picture data in a coded data buffer. Re-encoding of the selected inset picture data in this manner greatly reduces data storage requirements and simplifies the circuitry required to subsequently decode the inset picture data. To reduce frame memory requirements inset picture data is downsampled, stored and then upsampled prior to display thereby reducing inset picture frame memory buffer requirements.

摘要翻译： 描述适用于图像解码器的实现高效视频解码器。 在一个实施例中，视频解码器接收主要和次要比特流，其中次要比特流包括旨在被显示为插图的视频数据。 解码器在时间共享的基础上使用许多相同的电路组件来解码主图像和插图，以减少实现解码器所需的电路的数量。 在一个实施例中，准备器丢弃次级比特流中的大多数DCT系数，并且剩余数据被可变长度解码，然后在将插入图像数据存储在编码数据缓冲器中之前使用非MPEG兼容编码方案进行可变长度编码。 以这种方式重新编码所选择的插图图像数据大大减少了数据存储要求，并且简化了随后解码嵌入图像数据所需的电路。 为了减少帧存储器要求，画面数据被下采样，存储，然后在显示之前进行上采样，从而减少对画面帧存储器缓冲器的要求。

公开(公告)号：US20120287339A1

公开(公告)日：2012-11-15

申请号：US13558709

申请日：2012-07-26

申请人： Larry Pearlstein ,  Min Wang ,  Marinko Karanovic

发明人： Larry Pearlstein ,  Min Wang ,  Marinko Karanovic

IPC分类号： H04N7/01

CPC分类号： H04N7/014 ,  H04N7/0127

摘要： An image processing engine, comprising: a frame rate conversion entity configured to: (a) generate output pictures from input pictures, the output pictures comprising a set of first output pictures and a plurality of sets of second output pictures, each set of second output pictures being associated with one of the first output pictures, each of the first output pictures being derived from a respective one of the input pictures; and (b) control generation of the set of second output pictures associated with a particular first output picture based upon repetitive pattern presence detection within a related picture that is either (i) the particular first output picture or (ii) the input picture from which the particular first output picture was derived.

摘要翻译： 一种图像处理引擎，包括：帧速率转换实体，其被配置为：（a）从输入图像生成输出图像，所述输出图像包括一组第一输出图像和多组第二输出图像，每组第二输出 图像与第一输出图像之一相关联，每个第一输出图像从相应的输入图像中导出; （b）基于在（i）特定的第一输出图像或（ii）输入图像中的相关图像内的重复模式存在检测来控制与特定第一输出图像相关联的第二输出图像集合的生成， 导出了特定的第一个输出图像。

公开(公告)号：US08253854B2

公开(公告)日：2012-08-28

申请号：US12511697

申请日：2009-07-29

申请人： Larry Pearlstein ,  Min Wang ,  Marinko Karanovic

发明人： Larry Pearlstein ,  Min Wang ,  Marinko Karanovic

IPC分类号： H04N7/01

CPC分类号： H04N7/014 ,  H04N7/0127

摘要： An image processing engine, comprising: a frame rate conversion entity configured to: (a) generate output pictures from input pictures, the output pictures comprising a set of first output pictures and a plurality of sets of second output pictures, each set of second output pictures being associated with one of the first output pictures, each of the first output pictures being derived from a respective one of the input pictures; and (b) control generation of the set of second output pictures associated with a particular first output picture based upon repetitive pattern presence detection within a related picture that is either (i) the particular first output picture or (ii) the input picture from which the particular first output picture was derived.

摘要翻译： 一种图像处理引擎，包括：帧速率转换实体，其被配置为：（a）从输入图像生成输出图像，所述输出图像包括一组第一输出图像和多组第二输出图像，每组第二输出 图像与第一输出图像之一相关联，每个第一输出图像从相应的输入图像中导出; （b）基于在（i）特定的第一输出图像或（ii）输入图像中的相关图像内的重复模式存在检测来控制与特定第一输出图像相关联的第二输出图像集合的生成， 导出了特定的第一个输出图像。

公开(公告)号：US20120154527A1

公开(公告)日：2012-06-21

申请号：US13009946

申请日：2011-01-20

申请人： Priya Dwivedula ,  Michael Erwin ,  Eric Klings ,  Paul Gehman ,  Larry Pearlstein

发明人： Priya Dwivedula ,  Michael Erwin ,  Eric Klings ,  Paul Gehman ,  Larry Pearlstein

IPC分类号： H04N13/00

CPC分类号： H04N13/139 ,  H04N13/282

摘要： A 3-dimensional (3D) video rendering device may convert a first left view video of a decompressed 3D video having a first frame rate to generate a second left view video having a second frame rate, and convert a first right view video having the first frame rate to generate a second right view video having the second frame rate. The second left view video having a particular pixel resolution may be converted by the 3D video rendering device to generate a third left view video having full pixel resolution of the decompressed 3D video. The second right view video having the particular pixel resolution may be converted to generate a third right view video having the full pixel resolution. The 3D video rendering device may generate a sequence of video frames for 3D video display based on the third left view video and the third right view video.

摘要翻译： 三维（3D）视频呈现设备可以转换具有第一帧速率的解压缩3D视频的第一左视图视频以生成具有第二帧速率的第二左视图视频，并且转换具有第一帧速率的第一右视图视频 帧率以产生具有第二帧速率的第二右视图视频。 具有特定像素分辨率的第二左视图视频可以由3D视频呈现设备转换以产生具有解压缩3D视频的全像素分辨率的第三左视图视频。 可以转换具有特定像素分辨率的第二右视图视频以产生具有全像素分辨率的第三右视图视频。 3D视频呈现设备可以基于第三左视图视频和第三右视图视频来生成用于3D视频显示的视频帧序列。

公开(公告)号：US08126050B2

公开(公告)日：2012-02-28

申请号：US12497446

申请日：2009-07-02

申请人： Jill MacDonald Boyce ,  Larry Pearlstein

发明人： Jill MacDonald Boyce ,  Larry Pearlstein

IPC分类号： H04N11/02 ,  H04N7/12

CPC分类号： H04N19/00 ,  G06T3/40 ,  G06T3/4007 ,  G06T3/4084 ,  G11B5/0086 ,  G11B15/125 ,  G11B15/1875 ,  G11B15/4673 ,  H04N5/4401 ,  H04N5/45 ,  H04N5/46 ,  H04N5/78263 ,  H04N9/8042 ,  H04N9/8227 ,  H04N19/13 ,  H04N19/30 ,  H04N19/40 ,  H04N19/42 ,  H04N19/423 ,  H04N19/59 ,  H04N19/61 ,  H04N19/91 ,  H04N21/23106 ,  H04N21/2343 ,  H04N21/236 ,  H04N21/2662 ,  H04N21/4316 ,  H04N21/4325 ,  H04N21/434 ,  H04N21/4382 ,  H04N21/4402 ,  H04N21/440254 ,  H04N21/440263 ,  H04N21/4621

摘要： Methods and apparatus for implementing a reduced cost HDTV/SDTV video decoder are disclosed. The described joint video decoder is capable of decoding HDTV pictures at approximately the resolution of standard definition television pictures and can be used to decode HDTV and/or SDTV pictures. The described video decoder may be used as part of a picture-in-picture decoder circuit for providing picture-in-picture capability without providing multiple full resolution video decoders. The reduction in decoder circuit complexity is achieved through the use of a plurality of data reduction techniques including the use of a preparser, downsampling, and truncating pixel values.

摘要翻译： 公开了实现降低成本的HDTV / SDTV视频解码器的方法和装置。 所描述的联合视频解码器能够以大约分辨率的标准清晰度电视图像解码HDTV图像，并且可以用于解码HDTV和/或SDTV图像。 所描述的视频解码器可以用作画中画解码器电路的一部分，用于在不提供多个全分辨率视频解码器的情况下提供画中画能力。 解码器电路复杂度的降低通过使用多种数据简化技术来实现，包括使用预备器，下采样和截取像素值。

公开(公告)号：US20100026888A1

公开(公告)日：2010-02-04

申请号：US12511697

申请日：2009-07-29

申请人： Larry Pearlstein ,  Min Wang ,  Marinko Karanovic

发明人： Larry Pearlstein ,  Min Wang ,  Marinko Karanovic

IPC分类号： H04N7/01

CPC分类号： H04N7/014 ,  H04N7/0127

摘要： An image processing engine, comprising: a frame rate conversion entity configured to: (a) generate output pictures from input pictures, the output pictures comprising a set of first output pictures and a plurality of sets of second output pictures, each set of second output pictures being associated with one of the first output pictures, each of the first output pictures being derived from a respective one of the input pictures; and (b) control generation of the set of second output pictures associated with a particular first output picture based upon repetitive pattern presence detection within a related picture that is either (i) the particular first output picture or (ii) the input picture from which the particular first output picture was derived.

摘要翻译： 一种图像处理引擎，包括：帧速率转换实体，其被配置为：（a）从输入图像生成输出图像，所述输出图像包括一组第一输出图像和多组第二输出图像，每组第二输出 图像与第一输出图像之一相关联，每个第一输出图像从相应的输入图像中导出; （b）基于在（i）特定的第一输出图像或（ii）输入图像中的相关图像内的重复模式存在检测来控制与特定第一输出图像相关联的第二输出图像集合的生成， 导出了特定的第一个输出图像。

公开(公告)号：US20070139228A1

公开(公告)日：2007-06-21

申请号：US11538336

申请日：2006-10-03

申请人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

发明人： Larry Pearlstein ,  Richard Sita ,  Richard Selvaggi

IPC分类号： H03M7/00

CPC分类号： H03M7/40

摘要： An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored in the coefficient memory. Advantageously, the lookup tables may be altered to adapt the apparatus for processing variable length coded data to handle encoding or decoding video adhering to a specific standard. Furthermore, the lookup tables may be adapted to accelerate the determination of the presence of escape codes and the subsequent handling of the escape codes.

摘要翻译： 用于处理可变长度编码数据的装置包括系数缓冲器单元和若干查找表。 系数缓冲单元包括系数存储器和索引寄存器，用于存储系数存储器中存储的系数的非零性质的指示。 有利地，可以改变查找表以适应用于处理可变长度编码数据的装置，以处理遵守特定标准的编码或解码视频。 此外，查找表可以适于加速对转义码的存在的确定和随后的转义码的处理。