公开(公告)号：US07903015B1

公开(公告)日：2011-03-08

申请号：US12546521

申请日：2009-08-24

申请人： Rahmi Hezar ,  Lars Risbo

发明人： Rahmi Hezar ,  Lars Risbo

IPC分类号： H03M1/82

CPC分类号： H03M3/506 ,  H03M3/416 ,  H03M3/504

摘要： An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at an analog output of the cascaded circuit. Each of the cascade circuits contains a noise-shaping circuit, a PCM (Pulse Code Modulation)-to-PWM (Pulse Width Modulation) converter and a 1-bit P-tap AFIR (Analog Finite Impulse Response) filter DAC. Noise at the output of the cascaded circuit may be further reduced by increasing the number of cascade circuits.

摘要翻译： 本发明的实施例提供了一个或多个级联在一起以形成级联电路的级联电路。 级联电路降低级联电路模拟输出的噪声。 每个级联电路包含噪声整形电路，PCM（脉冲编码调制）到PWM（脉宽调制）转换器和1位P抽头AFIR（模拟有限脉冲响应）滤波器DAC。 可以通过增加级联电路的数量来进一步减少级联电路的输出端的噪声。

公开(公告)号：US20110043398A1

公开(公告)日：2011-02-24

申请号：US12546521

申请日：2009-08-24

申请人： Rahmi Hezar ,  Lars Risbo

发明人： Rahmi Hezar ,  Lars Risbo

IPC分类号： H03M3/00

CPC分类号： H03M3/506 ,  H03M3/416 ,  H03M3/504

摘要： An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at an analog output of the cascaded circuit. Each of the cascade circuits contains a noise-shaping circuit, a PCM (Pulse Code Modulation)-to-PWM (Pulse Width Modulation) converter and a 1-bit P-tap AFIR (Analog Finite Impulse Response) filter DAC. Noise at the output of the cascaded circuit may be further reduced by increasing the number of cascade circuits.

摘要翻译： 本发明的实施例提供了一个或多个级联在一起以形成级联电路的级联电路。 级联电路降低级联电路模拟输出的噪声。 每个级联电路包含噪声整形电路，PCM（脉冲编码调制）到PWM（脉宽调制）转换器和1位P抽头AFIR（模拟有限脉冲响应）滤波器DAC。 可以通过增加级联电路的数量来进一步减少级联电路的输出端的噪声。

公开(公告)号：US20060044057A1

公开(公告)日：2006-03-02

申请号：US10928528

申请日：2004-08-26

申请人： Rahmi Hezar ,  Baher Haroun ,  Brett Forejt ,  Srinath Ramaswamy

发明人： Rahmi Hezar ,  Baher Haroun ,  Brett Forejt ,  Srinath Ramaswamy

IPC分类号： H03F3/38

CPC分类号： H03F3/2173 ,  H03F1/34 ,  H03F3/217 ,  H03F2200/331

摘要： An amplifier having an active and passive gain stage connect to a load for driving a load according to a system analog input. A first embodiment of the amplifier in accordance with the present invention includes a logic network connected between a comparator network and a switching system, wherein the comparator network connects to the passive gain stage. Specifically, the active gain stage may include an active filter connected to receive an analog or digital input and provide a difference between the analog or digital input and the feedback signal relative to the gain factor of a gain unit connected to the active filter. The passive gain stage includes a passive filter. The logic network generates at least one switching signal which controls the switching system that includes at least one switching device to selectively provide power to the load. An output signal from the switching system provides output for the amplifier and is fed back to the active gain stage. In another embodiment, the output is a two-level signal and the passive and active filters are second order low pass filters, where the gain factor is about 25 or more. In yet another embodiment, the gain factor is approximately 250. Moreover, the amplifier may include a digital delta-sigma modulator connected to supply a two level input.

摘要翻译： 具有有源和无源增益级的放大器根据系统模拟输入连接到用于驱动负载的负载。 根据本发明的放大器的第一实施例包括连接在比较器网络和交换系统之间的逻辑网络，其中比较器网络连接到被动增益级。 具体地，有源增益级可以包括连接到接收模拟或数字输入的有源滤波器，并且相对于连接到有源滤波器的增益单元的增益因子，提供模拟或数字输入与反馈信号之间的差异。 被动增益级包括无源滤波器。 逻辑网络生成至少一个切换信号，其控制包括至少一个开关装置的开关系统以选择性地向负载提供电力。 来自开关系统的输出信号为放大器提供输出并反馈到有源增益级。 在另一个实施例中，输出是两电平信号，无源和有源滤波器是二阶低通滤波器，其中增益因子约为25或更大。 在另一个实施例中，增益因子为大约250.此外，放大器可以包括连接以提供两级输入的数字Δ-Σ调制器。

公开(公告)号：US06998910B2

公开(公告)日：2006-02-14

申请号：US10762819

申请日：2004-01-22

申请人： Rahmi Hezar ,  Baher Haroun

发明人： Rahmi Hezar ,  Baher Haroun

IPC分类号： H03F3/38

CPC分类号： H03F3/217 ,  H03F2200/331

摘要： An amplifier and a driver circuit therefor are presented for driving a load according to a system analog input. The amplifier comprises a passive delta-sigma modulator with a passive filter providing a first filtered signal according to a passive filter input and according to a feedback signal, a quantizer coupled with the passive filter and providing a quantized output according to the first filtered signal, and a switching system coupled with the the passive filter and the quantizer. The switching system selectively providing power to a load according to the quantized output and provides the feedback signal to the passive input, wherein a gain amplifier is provided in a feedback loop around the passive delta-sigma modulator.

摘要翻译： 介绍放大器及其驱动电路，用于根据系统模拟输入驱动负载。 该放大器包括无源Δ-Σ调制器，无源滤波器根据无源滤波器输入提供第一滤波信号，并根据反馈信号，与无源滤波器耦合的量化器，并根据第一滤波信号提供量化输出， 以及与无源滤波器和量化器耦合的开关系统。 开关系统根据量化的输出选择性地向负载提供电力，并将反馈信号提供给无源输入，其中增益放大器设置在无源Δ-Σ调制器周围的反馈回路中。

公开(公告)号：US08456341B2

公开(公告)日：2013-06-04

申请号：US13134301

申请日：2011-06-03

申请人： Rahmi Hezar ,  Baher Haroun ,  Halil Kiper ,  Mounir Fares ,  Ajay Kumar

发明人： Rahmi Hezar ,  Baher Haroun ,  Halil Kiper ,  Mounir Fares ,  Ajay Kumar

IPC分类号： H03M1/66

CPC分类号： H03M1/66 ,  H03M1/747 ,  H03M3/464

摘要： A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices. The current source for each DAC segment is diverted to ground, the M-node, or the P-node depending on the value of the 3-level control signal.

摘要翻译： 一种用于处理信号的系统包括：检测器，被配置为检测两级比特流; 转换器，被配置为基于所述两级比特流内的两个相邻值生成三电平控制信号; 以及开关，被配置为基于三电平控制信号的值来确定三个不同路径中的哪一个耦合电流源。 因此，基于输出流的相邻值，生成三电平控制信号，其控制电流源与三个不同路径之一的耦合。 这种类型的三电平数模转换器可以是例如模数转换器的反馈回路的一部分。 类似技术也可以用在多段数模转换器中，其中DAC的每个段由3电平控制信号控制，并且使用PMOS器件来实现DAC。 每个DAC段的电流源根据3电平控制信号的值转移到地，M节点或P节点。

公开(公告)号：US20120306678A1

公开(公告)日：2012-12-06

申请号：US13134301

申请日：2011-06-03

申请人： Rahmi Hezar ,  Baher Haroun ,  Halil Kiper ,  Mounir Fares ,  Ajay Kumar

发明人： Rahmi Hezar ,  Baher Haroun ,  Halil Kiper ,  Mounir Fares ,  Ajay Kumar

IPC分类号： H03M1/72

CPC分类号： H03M1/66 ,  H03M1/747 ,  H03M3/464

摘要： A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices. The current source for each DAC segment is diverted to ground, the M-node, or the P-node depending on the value of the 3-level control signal.

摘要翻译： 一种用于处理信号的系统包括：检测器，被配置为检测两级比特流; 转换器，被配置为基于所述两级比特流内的两个相邻值生成三电平控制信号; 以及开关，被配置为基于三电平控制信号的值来确定三个不同路径中的哪一个耦合电流源。 因此，基于输出流的相邻值，生成三电平控制信号，其控制电流源与三个不同路径之一的耦合。 这种类型的三电平数模转换器可以是例如模数转换器的反馈回路的一部分。 类似的技术也可以用在多段数模转换器中，其中DAC的每个段由3电平控制信号控制，并且使用PMOS器件实现DAC。 每个DAC段的电流源根据3电平控制信号的值转移到地，M节点或P节点。

公开(公告)号：US07924191B2

公开(公告)日：2011-04-12

申请号：US12495427

申请日：2009-06-30

申请人： Rahmi Hezar

发明人： Rahmi Hezar

IPC分类号： H03M3/00

CPC分类号： H03M3/47

摘要： A sigma delta analog to digital converter includes a clock operating at a conversion clock rate and first and second conversion paths. The first path includes a first sigma delta modulator configured to produce from an input analog signal a first bit stream at the clock rate, and a first digital filter configured to decimate the first bit stream. The second conversion path has a second sigma delta modulator configured to produce from the input analog signal a second bit stream separate from the first bit stream at the clock rate, and a second digital filter configured to decimate the second bit stream.

摘要翻译： Σ-Δ模数转换器包括以转换时钟速率和第一和第二转换路径工作的时钟。 第一路径包括被配置为以时钟速率从输入模拟信号产生第一位流的第一Σ-Δ调制器和被配置为抽取第一位流的第一数字滤波器。 第二转换路径具有第二Σ-Δ调制器，其被配置为从输入模拟信号产生以时钟速率与第一比特流分离的第二比特流，以及被配置为抽取第二比特流的第二数字滤波器。

公开(公告)号：US06940436B2

公开(公告)日：2005-09-06

申请号：US10698830

申请日：2003-10-31

申请人： Rahmi Hezar ,  Oguz Altun

发明人： Rahmi Hezar ,  Oguz Altun

IPC分类号： H03M3/04 ,  H03M7/00 ,  H03M3/00

CPC分类号： H03M3/412 ,  H03M3/436 ,  H03M3/456 ,  H03M7/3042

摘要： A analog-to-digital converters and second order noise shaping systems are presented for providing a noise shaped analog feedback signal to a A/D converter in an analog-to-digital conversion system. The noise shaping system comprises a first order integrator having a single amplifier, and a digital error feedback system comprising a digital signal processing system, in which the digital error feedback system provides an analog feedback signal to the A/D converter with second order noise shaping with respect to a quantization error associated with the A/D converter.

公开(公告)号：US20050116850A1

公开(公告)日：2005-06-02

申请号：US10699585

申请日：2003-10-31

申请人： Rahmi Hezar ,  Baher Haroun

发明人： Rahmi Hezar ,  Baher Haroun

IPC分类号： H03M3/00 ,  H03M3/02

CPC分类号： H03M3/322 ,  H03M3/43 ,  H03M3/454

摘要： A fourth order delta sigma analog-to-digital converter is presented, comprising a passive delta sigma modulator including a passive filter, a quantizer, and a digital-to-analog converter in a first feedback loop, and an active filter having a large gain factor in a second feedback loop around the passive delta-sigma modulator.

摘要翻译： 提出了一种第四级ΔΣ模数转换器，包括在第一反馈回路中包括无源滤波器，量化器和数模转换器的无源Δ-Σ调制器和具有大增益的有源滤波器 在被动Δ-Σ调制器周围的第二反馈环路中的因子。

公开(公告)号：US20050093726A1

公开(公告)日：2005-05-05

申请号：US10698830

申请日：2003-10-31

申请人： Rahmi Hezar ,  Oguz Altun

发明人： Rahmi Hezar ,  Oguz Altun

IPC分类号： H03M3/04 ,  H03M7/00 ,  H03M3/00

CPC分类号： H03M3/412 ,  H03M3/436 ,  H03M3/456 ,  H03M7/3042

摘要： A analog-to-digital converters and second order noise shaping systems are presented for providing a noise shaped analog feedback signal to a A/D converter in an analog-to-digital conversion system. The noise shaping system comprises a first order integrator having a single amplifier, and a digital error feedback system comprising a digital signal processing system, in which the digital error feedback system provides an analog feedback signal to the A/D converter with second order noise shaping with respect to a quantization error associated with the A/D converter.

摘要翻译： 呈现了模数转换器和二阶噪声整形系统，用于在模数转换系统中向A / D转换器提供噪声形模拟反馈信号。 噪声整形系统包括具有单个放大器的一阶积分器和包括数字信号处理系统的数字误差反馈系统，其中数字误差反馈系统向A / D转换器提供具有二阶噪声整形的模拟反馈信号 关于与A / D转换器相关联的量化误差。