公开(公告)号：US06940436B2

公开(公告)日：2005-09-06

申请号：US10698830

申请日：2003-10-31

申请人： Rahmi Hezar ,  Oguz Altun

发明人： Rahmi Hezar ,  Oguz Altun

IPC分类号： H03M3/04 ,  H03M7/00 ,  H03M3/00

CPC分类号： H03M3/412 ,  H03M3/436 ,  H03M3/456 ,  H03M7/3042

摘要： A analog-to-digital converters and second order noise shaping systems are presented for providing a noise shaped analog feedback signal to a A/D converter in an analog-to-digital conversion system. The noise shaping system comprises a first order integrator having a single amplifier, and a digital error feedback system comprising a digital signal processing system, in which the digital error feedback system provides an analog feedback signal to the A/D converter with second order noise shaping with respect to a quantization error associated with the A/D converter.

公开(公告)号：US20050093726A1

公开(公告)日：2005-05-05

申请号：US10698830

申请日：2003-10-31

申请人： Rahmi Hezar ,  Oguz Altun

发明人： Rahmi Hezar ,  Oguz Altun

IPC分类号： H03M3/04 ,  H03M7/00 ,  H03M3/00

CPC分类号： H03M3/412 ,  H03M3/436 ,  H03M3/456 ,  H03M7/3042

摘要： A analog-to-digital converters and second order noise shaping systems are presented for providing a noise shaped analog feedback signal to a A/D converter in an analog-to-digital conversion system. The noise shaping system comprises a first order integrator having a single amplifier, and a digital error feedback system comprising a digital signal processing system, in which the digital error feedback system provides an analog feedback signal to the A/D converter with second order noise shaping with respect to a quantization error associated with the A/D converter.

摘要翻译： 呈现了模数转换器和二阶噪声整形系统，用于在模数转换系统中向A / D转换器提供噪声形模拟反馈信号。 噪声整形系统包括具有单个放大器的一阶积分器和包括数字信号处理系统的数字误差反馈系统，其中数字误差反馈系统向A / D转换器提供具有二阶噪声整形的模拟反馈信号 关于与A / D转换器相关联的量化误差。

公开(公告)号：US08831085B2

公开(公告)日：2014-09-09

申请号：US13327247

申请日：2011-12-15

申请人： Rahmi Hezar ,  Lei Ding ,  Joonhoi Hur ,  Baher S. Haroun

发明人： Rahmi Hezar ,  Lei Ding ,  Joonhoi Hur ,  Baher S. Haroun

IPC分类号： H03K7/08

CPC分类号： H04L1/0071 ,  H04B1/04

摘要： A method for transmitting radio frequency (RF) signals is provided. In-phase (I) and quadrature (Q) signals are received and filtered using sigma-delta modulation. I and Q pulse width modulation signals are generated from the filtered I and Q signals and interleaved so as to generate a time-interleaved signal. The time-interleaved signal is then amplified to generate the RF signals.

摘要翻译： 提供了一种用于发射射频（RF）信号的方法。 使用Σ-Δ调制接收和滤波同相（I）和正交（Q）信号。 从经滤波的I和Q信号产生I和Q脉宽调制信号并进行交织，以产生时间交织的信号。 然后对时间交织的信号进行放大以产生RF信号。

公开(公告)号：US20130234795A1

公开(公告)日：2013-09-12

申请号：US13416841

申请日：2012-03-09

申请人： Joonhoi Hur ,  Lei Ding ,  Rahmi Hezar ,  Baher S. Haroun

发明人： Joonhoi Hur ,  Lei Ding ,  Rahmi Hezar ,  Baher S. Haroun

IPC分类号： H03F3/217

CPC分类号： H03F3/2173 ,  H03F1/56 ,  H03F2200/387

摘要： A method is provided. A first enable signal is asserted so as to enable a first driver, where the first driver has a first output and a first parasitic capacitance. A second enable signal is asserted so as to enable a second driver, where the second driver has a second output and a second parasitic capacitance. The first and second outputs are coupled together by a switching network when the second driver is enabled. Pulses from complementary first and second radio frequency (RF) signals are applied to the first driver, where there is a first set of free-fly intervals between consecutive pulses from the first and second RF signals, and pulses from complementary third and fourth RF signals are applied to the second driver, wherein there is a second set of free-fly interval between consecutive pulses from the third and fourth RF signals.

摘要翻译： 提供了一种方法。 第一使能信号被确定为使第一驱动器能够使第一驱动器具有第一输出和第一寄生电容。 第二使能信号被确定为使第二驱动器能够启动，其中第二驱动器具有第二输出和第二寄生电容。 当第二驱动器被使能时，第一和第二输出由交换网络耦合在一起。 来自互补第一和第二射频（RF）信号的脉冲被施加到第一驱动器，其中在来自第一和第二RF信号的连续脉冲之间存在第一组自由飞行间隔，以及来自互补的第三和第四RF信号的脉冲 被施加到第二驱动器，其中在来自第三和第四RF信号的连续脉冲之间存在第二组自由间隔。

公开(公告)号：US20110267210A1

公开(公告)日：2011-11-03

申请号：US12769629

申请日：2010-04-28

申请人： Lars Risbo ,  Rahmi Hezar ,  Burak Kelleci ,  Anker Bjoern-Josefsen

发明人： Lars Risbo ,  Rahmi Hezar ,  Burak Kelleci ,  Anker Bjoern-Josefsen

IPC分类号： H03M1/00 ,  H03M1/66 ,  H03M3/00

CPC分类号： H03M7/3006 ,  H03M1/0668 ,  H03M1/74 ,  H03M3/502

摘要： A signal converting system is described that has a multi-segment digital to analog converter coupled to one or more error shaping loops. Each error shaping loop includes a quantizer with a feedback loop configured to generate a control signal responsive to a stream of symbols and to an error signal. Each error shaping loop also includes an inter-symbol-interference (ISI) shaping loop coupled to receive the control signal and to produce an ISI portion of the error signal that is responsive to inter-symbol transition rate.

摘要翻译： 描述了具有耦合到一个或多个错误整形环路的多段数模转换器的信号转换系统。 每个错误整形循环包括具有反馈回路的量化器，其被配置为响应于符号流和误差信号产生控制信号。 每个错误整形环路还包括码元间干扰（ISI）整形环路，其被耦合以接收控制信号并产生响应于符号间转换速率的误差信号的ISI部分。

公开(公告)号：US20100331039A1

公开(公告)日：2010-12-30

申请号：US12495427

申请日：2009-06-30

申请人： Rahmi Hezar

发明人： Rahmi Hezar

IPC分类号： H04L27/06 ,  H03M3/00 ,  H04M1/00

CPC分类号： H03M3/47

摘要： A sigma delta analog to digital converter includes a clock operating at a conversion clock rate and first and second conversion paths. The first path includes a first sigma delta modulator configured to produce from an input analog signal a first bit stream at the clock rate, and a first digital filter configured to decimate the first bit stream. The second conversion path has a second sigma delta modulator configured to produce from the input analog signal a second bit stream separate from the first bit stream at the clock rate, and a second digital filter configured to decimate the second bit stream.

摘要翻译： Σ-Δ模数转换器包括以转换时钟速率和第一和第二转换路径工作的时钟。 第一路径包括被配置为以时钟速率从输入模拟信号产生第一位流的第一Σ-Δ调制器和被配置为抽取第一位流的第一数字滤波器。 第二转换路径具有第二Σ-Δ调制器，其被配置为从输入模拟信号产生以时钟速率与第一比特流分离的第二比特流，以及被配置为抽取第二比特流的第二数字滤波器。

公开(公告)号：US20130241663A1

公开(公告)日：2013-09-19

申请号：US13421567

申请日：2012-03-15

申请人： Lei Ding ,  Rahmi Hezar ,  Joonhoi Hur ,  Baher S. Haroun

发明人： Lei Ding ,  Rahmi Hezar ,  Joonhoi Hur ,  Baher S. Haroun

IPC分类号： H03K7/08

CPC分类号： H03K7/08

摘要： A method is provided. An input signal is received, and a noise-shaped signal is generated from the input signal. The noise-shaped signal is formed from a plurality of noise-shaping levels. A pulse stream is generated from the noise-shaped signal over a plurality of periods, where each period has a plurality of frames. The pulse stream also includes a plurality of pulse sets, where each pulse set is associated with at least one of the noise-shaping levels, and, for each pulse set having a total pulse width for its period that is less than its period and greater than zero, each pulse set includes at least one pulse in each frame for its period.

摘要翻译： 提供了一种方法。 接收输入信号，并从输入信号产生噪声信号。 噪声形状信号由多个噪声整形电平形成。 在多个周期中，从噪声信号产生脉冲流，其中每个周期具有多个帧。 脉冲流还包括多个脉冲组，其中每个脉冲组与噪声整形电平中的至少一个相关联，并且对于每个具有小于其周期和更大周期的总脉冲宽度的脉冲集合 每个脉冲组在其周期中包括每帧中的至少一个脉冲。

公开(公告)号：US20130148760A1

公开(公告)日：2013-06-13

申请号：US13313971

申请日：2011-12-07

申请人： Rahmi Hezar ,  Lei Ding ,  Joonhoi Hur ,  Baher Haroun

发明人： Rahmi Hezar ,  Lei Ding ,  Joonhoi Hur ,  Baher Haroun

IPC分类号： H04L25/49

CPC分类号： H03F3/211 ,  H03F3/24 ,  H04L25/4902

摘要： A method for generating an amplified radio frequency (RF) signal is provided. In-phase (I) and quadrature (Q) signals are received and interleaved so as to generate a time-interleaved signal. Delayed time-interleaved signals are then generated from the time interleaved signal, and each of the delayed time-interleaved signals is amplified so as to generate a plurality of amplified signals. The amplified signals are then combined with a transformer, where the delayed time-interleaved signals are arranged to generate a filter response with the transformer.

摘要翻译： 提供了一种用于产生放大射频（RF）信号的方法。 接收和交织同相（I）和正交（Q）信号，以产生时间交织的信号。 然后从时间交织信号产生延迟的时间交织信号，并且每个延迟时间交织的信号被放大以产生多个放大的信号。 然后将放大的信号与变压器组合，其中延迟的时间交织信号被布置成产生与变压器的滤波器响应。

公开(公告)号：US06930624B2

公开(公告)日：2005-08-16

申请号：US10699585

申请日：2003-10-31

申请人： Rahmi Hezar ,  Baher Haroun

发明人： Rahmi Hezar ,  Baher Haroun

IPC分类号： H03M3/00 ,  H03M3/02

CPC分类号： H03M3/322 ,  H03M3/43 ,  H03M3/454

摘要： A fourth order delta sigma analog-to-digital converter is presented, comprising a passive delta sigma modulator including a passive filter, a quantizer, and a digital-to-analog converter in a first feedback loop, and an active filter having a large gain factor in a second feedback loop around the passive delta-sigma modulator.

摘要翻译： 提出了一种第四级ΔΣ模数转换器，包括在第一反馈回路中包括无源滤波器，量化器和数模转换器的无源Δ-Σ调制器和具有大增益的有源滤波器 在被动Δ-Σ调制器周围的第二反馈环路中的因子。

公开(公告)号：US08483856B2

公开(公告)日：2013-07-09

申请号：US12783290

申请日：2010-05-19

申请人： Rahmi Hezar ,  Baher Haroun

发明人： Rahmi Hezar ,  Baher Haroun

IPC分类号： G06F17/00

CPC分类号： H03M3/372 ,  H03M3/50

摘要： A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal.

摘要翻译： 电路包括数字振荡器，锁相环（PLL），数字信号发生器，校正电路和数模转换器DAC（DAC）。 数字振荡器可以输出参考时钟信号。 PLL可以基于参考时钟信号输出系统时钟信号。 数字信号发生器可以根据系统时钟信号输出数字信号。 校正电路可以基于参考时钟信号，系统时钟信号和数字信号输出预失真信号。 DAC可以根据预失真信号和系统时钟信号输出模拟信号。