公开(公告)号：US20070254443A1

公开(公告)日：2007-11-01

申请号：US11741034

申请日：2007-04-27

申请人： Huilong Zhu ,  Oleg Gluschenkov

发明人： Huilong Zhu ,  Oleg Gluschenkov

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/7624 ,  H01L29/66659 ,  H01L29/7835

摘要： A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.

摘要翻译： 场效应晶体管（FET）器件包括形成在半导体衬底上的栅极导体，具有在栅极导体下方重叠并延伸的源极延伸的源极区域以及具有与栅极导体下方重叠并延伸的漏极延伸的漏极区域 仅沿着栅极导体的宽度的选定位置。

公开(公告)号：US20070202639A1

公开(公告)日：2007-08-30

申请号：US11741441

申请日：2007-04-27

申请人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Omer Dokumaci ,  Bruce Doris ,  Oleg Gluschenkov ,  Huilong Zhu

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：US20070161169A1

公开(公告)日：2007-07-12

申请号：US11306710

申请日：2006-01-09

申请人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Oleg Gluschenkov

发明人： Michael P. Belyansky ,  Dureseti Chidambarrao ,  Oleg Gluschenkov

IPC分类号： H01L21/8234

CPC分类号： H01L29/0653 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/78609 ,  Y10S438/954

摘要： A field effect transistor (FET) device includes a gate conductor and gate dielectric formed over an active device area of a semiconductor substrate. A drain region is formed in the active device area of the semiconductor substrate, on one side of the gate conductor, and a source region is formed in the active device area of the semiconductor substrate, on an opposite side of the gate conductor. A dielectric halo or plug is formed in the active area of said semiconductor substrate, the dielectric halo or plug disposed in contact between the drain region and a body region, and in contact between the source region and the body region.

摘要翻译： 场效应晶体管（FET）器件包括在半导体衬底的有源器件区域上形成的栅极导体和栅极电介质。 在半导体衬底的有源器件区域中，在栅极导体的一侧上形成漏极区域，并且在栅极导体的相对侧上在半导体衬底的有源器件区域中形成源极区域。 在所述半导体衬底的有源区域中形成介电晕或插塞，所述介电晕或插头设置在所述漏区和体区之间并且在所述源区与所述体区之间接触。

公开(公告)号：US07205206B2

公开(公告)日：2007-04-17

申请号：US10708430

申请日：2004-03-03

申请人： Michael P. Belyansky ,  Bruce B. Doris ,  Oleg Gluschenkov

发明人： Michael P. Belyansky ,  Bruce B. Doris ,  Oleg Gluschenkov

IPC分类号： H01L21/76

CPC分类号： H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

摘要： Compressive or tensile materials are selectively introduced beneath and in alignment with spacer areas and adjacent to channel areas of a semiconductor substrate to enhance or degrade electron and hole mobility in CMOS circuits. A process entails steps of creating dummy spacers, forming a dielectric mandrel (i.e., mask), removing the dummy spacers, etching recesses into the underlying semiconductor substrate, introducing a compressive or tensile material into a portion of each recess, and filling the remainder of each recess with substrate material.

摘要翻译： 压缩或拉伸材料被选择性地引入到间隔区域的下方并且与半导体衬底的通道区域相邻并且与CMOS电路中的电子和空穴迁移率相关联。 一个过程需要创建虚拟间隔物的步骤，形成介质心轴（即掩模），去除虚拟间隔物，将凹槽蚀刻到下面的半导体衬底中，将压缩或拉伸材料引入每个凹部的一部分中， 每个凹槽与基底材料。

公开(公告)号：US20070063277A1

公开(公告)日：2007-03-22

申请号：US11162778

申请日：2005-09-22

申请人： Michael Belyansky ,  Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

发明人： Michael Belyansky ,  Dureseti Chidambarrao ,  Omer Dokumaci ,  Oleg Gluschenkov

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L29/512 ,  H01L21/26586 ,  H01L21/31155 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

摘要： The present invention provides a semiconductor structure having at least one CMOS device in which the Miller capacitances, i.e., overlap capacitances, are reduced and the drive current is improved. The inventive structure includes a semiconductor substrate having at least one overlaying gate conductor, each of the at least one overlaying gate conductors has vertical edges; a first gate oxide located beneath the at least one overlaying gate conductor, the first gate oxide not extending beyond the vertical edges of the at least overlaying gate conductor; and a second gate oxide located beneath at least a portion of the at one overlaying gate conductor. In accordance with the present invention, the first gate oxide and the second gate oxide are selected from high k oxide-containing materials and low k oxide-containing materials, with the proviso that when the first gate oxide is high k, than the second gate oxide is low k, or when the first gate oxide is low k, than the second gate oxide is high k.

摘要翻译： 本发明提供一种具有至少一个CMOS器件的半导体结构，其中米勒电容（即，重叠电容）被减小并且驱动电流得到改善。 本发明的结构包括具有至少一个覆盖栅极导体的半导体衬底，所述至少一个覆盖栅极导体中的每一个具有垂直边缘; 位于所述至少一个覆盖栅极导体下方的第一栅极氧化物，所述第一栅极氧化物不延伸超过所述至少覆盖栅极导体的垂直边缘; 以及位于一个重叠栅极导体的至少一部分下方的第二栅极氧化物。 根据本发明，第一栅极氧化物和第二栅极氧化物选自含高K氧化物的材料和低K氧化物的材料，条件是当第一栅极氧化物高于第二栅极 氧化物为低k，或者当第一栅极氧化物为低k时，第二栅极氧化物为高k。

公开(公告)号：US20070032028A1

公开(公告)日：2007-02-08

申请号：US11161447

申请日：2005-08-03

申请人： Huilong Zhu ,  Oleg Gluschenkov

发明人： Huilong Zhu ,  Oleg Gluschenkov

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/7624 ,  H01L29/66659 ,  H01L29/7835

摘要： A field effect transistor (FET) device includes a gate conductor formed over a semiconductor substrate, a source region having a source extension that overlaps and extends under the gate conductor, and a drain region having a drain extension that overlaps and extends under the gate conductor only at selected locations along the width of the gate conductor.

摘要翻译： 场效应晶体管（FET）器件包括形成在半导体衬底上的栅极导体，具有在栅极导体下方重叠并延伸的源极延伸的源极区域以及具有与栅极导体下方重叠并延伸的漏极延伸的漏极区域 仅沿着栅极导体的宽度的选定位置。

公开(公告)号：US07084024B2

公开(公告)日：2006-08-01

申请号：US10711642

申请日：2004-09-29

申请人： Oleg Gluschenkov ,  Dae-Gyu Park

发明人： Oleg Gluschenkov ,  Dae-Gyu Park

IPC分类号： H01L21/8238

CPC分类号： H01L21/28079 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/518

摘要： Methods related to formation of a gate electrode are disclosed that employ a conductive hard mask as a protective layer during a photoresist removal process. In preferred embodiments, the conductive hard mask includes a metal containing conductor or a metal silicide. The invention prevents process damage on the gate dielectric during wet and/or dry resist strip, and since the conductive hard mask cannot be etched in typical resist strip chemistries, the invention also protects a metal electrode under the hard mask. The steps disclosed allow creation of a multiple work function metal gate electrode, or a mixed metal and polysilicon gate electrode, which do not suffer from the problems of the related art.

摘要翻译： 公开了在光致抗蚀剂去除过程中使用导电硬掩模作为保护层的与栅电极的形成有关的方法。 在优选实施例中，导电硬掩模包括含金属的导体或金属硅化物。 本发明防止了在湿式和/或干式抗蚀剂条带期间对栅极电介质的工艺损伤，并且由于导电硬掩模不能在典型的抗蚀剂条纹化学中被蚀刻，本发明还保护硬掩模下面的金属电极。 所公开的步骤允许创建不具有现有技术问题的多功能金属栅电极或混合金属和多晶硅栅电极。

公开(公告)号：US20060108651A1

公开(公告)日：2006-05-25

申请号：US10904660

申请日：2004-11-22

申请人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

发明人： Huilong Zhu ,  Lawrence Clevenger ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Kaushik Kumar ,  Carl Radens ,  Dureseti Chidambarrao

IPC分类号： H01L29/94

CPC分类号： H01L21/26506 ,  H01L21/26586 ,  H01L29/0843 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： A novel transistor structure and method for fabrication the same. The novel transistor structure comprises first and second source/drain (S/D) regions whose top surfaces are lower than a top surface of the channel region of the transistor structure. The method for fabricating the transistor structure starts out with a planar semiconductor layer and a gate stack on top of the semiconductor layer. Then, top regions of the semiconductor layer on opposing sides of the gate stack are removed. Then, regions beneath the removed regions are doped to form lowered S/D regions of the transistor structure

摘要翻译： 一种新颖的晶体管结构及其制造方法。 新颖的晶体管结构包括顶表面低于晶体管结构的沟道区的顶表面的第一和第二源极/漏极（S / D）区域。 用于制造晶体管结构的方法从在半导体层顶部的平面半导体层和栅叠层开始。 然后，去除栅极堆叠的相对侧上的半导体层的顶部区域。 然后，去除区域下方的区域被掺杂以形成晶体管结构的降低的S / D区域

公开(公告)号：US20060105516A1

公开(公告)日：2006-05-18

申请号：US11318818

申请日：2005-12-27

申请人： Michael Belyansky ,  Diane Boyd ,  Bruce Doris ,  Oleg Gluschenkov

发明人： Michael Belyansky ,  Diane Boyd ,  Bruce Doris ,  Oleg Gluschenkov

IPC分类号： H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

摘要： A method is provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A method is further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

摘要翻译： 提供了一种方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。

公开(公告)号：US20060076627A1

公开(公告)日：2006-04-13

申请号：US10711899

申请日：2004-10-12

申请人： Huajie Chen ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Werner Rausch

发明人： Huajie Chen ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Werner Rausch

IPC分类号： H01L29/94

CPC分类号： H01L21/26533 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/31654 ,  H01L21/31675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/66636

摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅​​衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。