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21.发明授权公开(公告)号：US07691714B2
公开(公告)日：2010-04-06
申请号：US11042415
申请日：2005-01-25
IPC分类号： H01L21/336 , H01L21/337
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/823814 , H01L21/823871
摘要： The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.
摘要翻译： 本发明提供了晶体管器件的制造方法，集成电路的制造方法以及晶体管器件。 制造晶体管器件的方法以及其他步骤包括在衬底上形成栅极结构，并在栅极结构附近形成衬底中的源极/漏极区域，源极/漏极区域具有与衬底形成电连接的边界 。 该方法还包括在衬底中形成位错环，位错环不延伸到源/漏区的边界之外。
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公开(公告)号：US20090174005A1
公开(公告)日：2009-07-09
申请号：US12408992
申请日：2009-03-23
IPC分类号： H01L27/092 , H01L29/06 , H01L21/4763
CPC分类号： H01L21/30608 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.
摘要翻译： 半导体器件包括半导体衬底上的栅极结构和半导体衬底中的凹陷区域。 凹陷区域具有接近半导体衬底的顶表面的最宽的侧向开口。 最宽的侧向开口会削弱门结构。
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23.发明授权Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process 有权在EPI过程期间选择性地保护NMOS区域，PMOS区域和栅极层的方法公开(公告)号：US07514309B2
公开(公告)日：2009-04-07
申请号：US11184337
申请日：2005-07-19
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner is formed on the gate electrode layer. A resist mask is formed that defines gate structures. The gate electrode layer is patterned to form the gate structures. Offset spacers are formed on lateral edges of the gate structures and extension regions are then formed in the well regions. Sidewall spacers are then formed on the lateral edges of the gate structures. An NMOS protective region layer is formed that covers the NMOS region of the device. A recess etch is performed within the PMOS region followed by formation of strain inducing recess structures.
摘要翻译： 制造具有保护衬垫和/或层的半导体器件。 阱区和隔离区形成在半导体本体内。 栅电介质层形成在半导体本体上。 在栅极电介质层上形成诸如多晶硅的栅电极层。 在栅电极层上形成保护栅衬。 形成限定栅极结构的抗蚀剂掩模。 图案化栅极电极层以形成栅极结构。 偏移间隔件形成在栅极结构的横向边缘上，然后在阱区域中形成延伸区域。 然后在门结构的侧边缘上形成侧壁间隔物。 形成覆盖器件的NMOS区域的NMOS保护区域层。 在PMOS区域内执行凹陷蚀刻，随后形成应变引发凹陷结构。
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24.发明授权Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon 有权通过并入碳来减少晶体管栅极到源极/漏极重叠电容的方法公开(公告)号：US07199011B2
公开(公告)日：2007-04-03
申请号：US10620492
申请日：2003-07-16
IPC分类号： H01L21/336
CPC分类号： H01L21/28044 , H01L21/26506 , H01L21/28114 , H01L21/32137 , H01L29/42376
摘要： The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.
摘要翻译： 本发明涉及以减轻重叠电容的方式形成晶体管，从而有利于提高切换速度。 更具体地，晶体管的栅极堆叠形成为包括任选的多晶硅层和多晶硅层，其中至少一个或多个层包含碳。 堆叠还可以包括也可以包含碳的多晶硅种子层。 碳改变侧壁钝化材料的组分并影响蚀刻过程中的蚀刻速率，从而促进各向同性蚀刻。 与蚀刻过程中使用的蚀刻剂相比，改变的钝化材料与多晶硅和掺杂碳的多晶硅层的增强灵敏度相结合，使堆叠具有缺口外观。 栅极堆叠的锥形配置对于可能在栅极结构下迁移以与堆叠中的导电层重叠的掺杂剂提供很小的（如果有的话）区域，并且因此减轻了重叠电容出现的机会。
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25.发明授权公开(公告)号：US07088123B1
公开(公告)日：2006-08-08
申请号：US11217144
申请日：2005-08-31
IPC分类号： G01R31/02
CPC分类号： G01R31/2601 , G01R31/2648 , G01R31/2839
摘要： In one embodiment, a method for extracting C-V characteristics of ultra-thin oxides includes coupling a device under test to a testing structure, in which the device under test includes a plurality of transistors. Alternatively, the device under test includes a plurality of varactors. The method further includes inputting a radio frequency signal of at least one GHz into the testing structure, de-embedding the parasitics of the testing structure, inputting a bias into the device under test, determining the capacitance density per gate width of the device under test, plotting capacitance density per gate width versus gate length to obtain a first curve, and determining a slope of the first curve. These steps are repeated for one or more additional biasing conditions, and the determined slopes are plotted on a capacitance density per voltage graph to obtain a C-V curve for the device under test.
摘要翻译： 在一个实施例中，一种用于提取超薄氧化物的C-V特性的方法包括将被测试器件耦合到测试结构，其中被测器件包括多个晶体管。 或者，被测器件包括多个变容二极管。 该方法还包括将至少一GHz的射频信号输入到测试结构中，解嵌入测试结构的寄生效应，将偏置输入到被测器件中，确定被测器件的每个门宽的电容密度 绘制每个栅极宽度对栅极长度的电容密度以获得第一曲线，并且确定第一曲线的斜率。 对于一个或多个附加偏置条件重复这些步骤，并且将确定的斜率绘制在每个电压图上的电容密度上，以获得被测器件的C-V曲线。
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公开(公告)号：US20060113604A1
公开(公告)日：2006-06-01
申请号：US11000715
申请日：2004-12-01
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76802 , H01L21/823475 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices (102) are presented along with fabrication methods (202) therefor, in which a conductive contact structure (116b) is formed with a lower contact surface (116c) having a lateral contact dimension (152), where the contact structure (116b) is at least partially coupled with a contact landing surface of a polysilicon structure (110) having a lateral contact landing surface dimension (150) that is less than about 140% of the lateral contact dimension (152) of the conductive contact structure (116b).
摘要翻译： 呈现半导体器件（102）及其制造方法（202），其中导电接触结构（116b）形成有具有侧面接触尺寸（152）的下接触表面（116c），其中接触结构 （116b）至少部分地与多晶硅结构（110）的接触着陆表面耦合，所述多晶硅结构具有小于所述导电接触件的横向接触尺寸（152）的约140％的横向接触着陆表面尺寸（150） 结构（116b）。
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公开(公告)号：US07026218B2
公开(公告)日：2006-04-11
申请号：US10865342
申请日：2004-06-10
IPC分类号： H01L21/336
CPC分类号： H01L29/4925 , H01L21/28035 , H01L21/2807
摘要： The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).
摘要翻译： 本发明涉及一种PMOS晶体管的形成，其中一层硅或SiGe抑制p型掺杂剂进入下面的栅介质层。 可以将p型掺杂剂添加到覆盖硅或SiGe层的栅电极材料中，并且可以向硅或SiGe层扩散。 硅或SiGe层可以形成为约5至120纳米的厚度，并掺杂有例如铟（In）的掺杂剂，以阻止p型掺杂剂通过硅或SiGe层。 掺杂剂可以在硅或SiGe层的界面附近与硅介电材料的下层之间的硅或SiGe层内具有峰值浓度。 允许栅电极掺杂有p型掺杂剂（例如硼）有助于以具有期望值（例如，与约4.8至约5.6电子伏特的费米能级一致）的相关功函数形成晶体管。
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