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公开(公告)号：US09348748B2
公开(公告)日：2016-05-24
申请号：US14578820
申请日：2014-12-22
发明人： Yu-Ming Chang , Hsiang-Pang Li , Hang-Ting Lue , Yuan-Hao Chang , Tei-Wei Kuo
CPC分类号： G06F12/0246 , G06F12/00 , G06F2212/1036 , G06F2212/7211 , G11C16/3495 , G11C29/4401
摘要： Technology is described that increases endurance of memory devices through heal leveling. Heal leveling is a lightweight solution to distribute healing cycles among memory blocks. Approaches described herein can accomplish heal leveling without introducing a large amount of overhead. Heal leveling significantly improves the access performance and the effective lifetime of memory blocks. By more evenly distributing the heal count it may not be necessary to directly apply wear leveling based on access counts of each block because each block will be more evenly accessed in the long run. Heal leveling may be performed by moving data that is seldom or never modified after creation, such as read-only files, to blocks having suffered the greatest number, or a high number, of healing cycles.
摘要翻译： 技术被描述为通过愈合平整来增加记忆装置的耐久性。 治疗矫正是一种轻量级的解决方案，可以在内存块之间分配愈合周期。 本文描述的方法可以在不引入大量开销的情况下完成愈合平整。 愈合程度显着提高了存储块的访问性能和有效寿命。 通过更均匀地分配治疗计数，可能不需要基于每个块的访问计数来直接应用磨损均衡，因为长期来看每个块将被更均匀地访问。 可以通过将创建后很少或从不修改的数据（例如只读文件）移动到遭受最大数量的块或大量愈合周期来执行愈合调平。
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公开(公告)号：US09305638B1
公开(公告)日：2016-04-05
申请号：US14526560
申请日：2014-10-29
发明人： Yu-Ming Chang , Yung-Chun Li , Chih-Chang Hsieh , Shih-Fu Huang , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
CPC分类号： G11C11/5628 , G11C7/1006 , G11C11/5642 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： Operation methods for a memory device is provided. An operation method for the memory device comprises programming the memory device as described in follows. Data are provided. The data comprise a plurality of codes. Each number of the codes is counted. Then, a mapping rule is generated according to each number of the codes. In the mapping rule, each of the codes is mapped to one of a plurality of verifying voltage levels which are sequentially arranged from low to high. After that, the data are programmed into the memory device according to the mapping rule.
摘要翻译： 提供了存储器件的操作方法。 存储器件的操作方法包括如下所述对存储器件进行编程。 提供数据。 数据包括多个代码。 每个代码数都被计数。 然后，根据代码的数量生成映射规则。 在映射规则中，每个代码被映射到从低到高顺序排列的多个验证电压电平之一。 之后，根据映射规则将数据编程到存储设备中。
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公开(公告)号：US12056361B2
公开(公告)日：2024-08-06
申请号：US17814888
申请日：2022-07-26
发明人： Wei-Chen Wang , Tse-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
CPC分类号： G06F3/0613 , G06F3/0644 , G06F3/0679
摘要： An embodiment of the present disclosure discloses a memory device. The memory device comprises a memory controller, a buffer and a memory array. The buffer is coupled to the memory controller or embedded in the memory controller. A storage space of the buffer is configured by the memory controller to include a plurality of groups. The memory array is coupled to the memory controller, and comprising a plurality of tiles. The groups are one-to-one corresponding to the tiles. Each of the groups is configured to store data to be written into the corresponding tile. The memory controller performs one or more write operations based on the groups.
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公开(公告)号：US11594277B2
公开(公告)日：2023-02-28
申请号：US17871811
申请日：2022-07-22
发明人： Shu-Yin Ho , Hsiang-Pang Li , Yao-Wen Kang , Chun-Feng Wu , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G11C11/54 , G06N3/06 , G06N3/08 , G06F7/544 , G11C11/4091 , G11C11/408 , G11C11/4094
摘要： A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.
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公开(公告)号：US20220359003A1
公开(公告)日：2022-11-10
申请号：US17871811
申请日：2022-07-22
发明人： Shu-Yin Ho , Hsiang-Pang Li , Yao-Wen Kang , Chun-Feng Wu , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G11C11/54 , G11C11/4091 , G11C11/408 , G06N3/06 , G06N3/08 , G06F7/544 , G11C11/4094
摘要： A method for neural network computation using adaptive data representation, adapted for a processor to perform multiply-and-accumulate operations on a memory having a crossbar architecture, is provided. The memory comprises multiple input and output lines crossing each other, multiple cells respectively disposed at intersections of the input and output lines, and multiple sense amplifiers respectively connected to the output lines. In the method, an input cycle of kth bits respectively in an input data is adaptively divided into multiple sub-cycles, wherein a number of the divided sub-cycles is determined according to a value of k. The kth bits of the input data are inputted to the input lines with the sub-cycles and computation results of the output lines are sensed by the sense amplifiers. The computation results sensed in each sub-cycle are combined to obtain the output data corresponding to the kth bits of the input data.
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公开(公告)号：US11042308B2
公开(公告)日：2021-06-22
申请号：US16742811
申请日：2020-01-14
发明人： Wei-Chen Wang , Ping-Hsien Lin , Tse-Yuan Wang , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G06F3/06 , G06F16/901 , G06F12/10
摘要： A memory management method includes: performing a bloom filtering operation on a plurality of logic block addresses to determine a read and written frequency of each of the logic block addresses; setting a first program/erase (P/E) cycle threshold and a second P/E cycle threshold value, wherein the first P/E cycle threshold value is smaller than the second P/E cycle threshold value; dividing each of physical memory blocks into a first type memory block, a second type memory block or a third type memory block according to the first P/E cycle threshold value and the second P/E cycle threshold value; and, allocating each of the logic block addresses to the first type memory block, the second type memory block or the third type memory block according to the read and written frequency of corresponding logic block addresses.
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公开(公告)号：US20190034118A1
公开(公告)日：2019-01-31
申请号：US15662348
申请日：2017-07-28
发明人： Hung-Sheng Chang , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G06F3/06
摘要： A data management method for a memory device includes: counting a system time; when at least a part of a block of the memory device is accessed or refreshed or programmed at first time, assigning a block number of the block to point to a maximum remaining retention time; when a first downgrade trigger time reaches, assigning the block number to point from the maximum remaining retention time to a medium remaining retention time; when a second downgrade trigger time reaches, assigning the block number to point from the medium remaining retention time to a minimum remaining retention time; and once the block number points to the minimum remaining retention time, refreshing the block and assigning the block number to point to the maximum remaining retention time.
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公开(公告)号：US20170147217A1
公开(公告)日：2017-05-25
申请号：US15093841
申请日：2016-04-08
发明人： Hung-Sheng Chang , Yu-Ming Chang , Hsiang-Pang Li , Yuan-Hao Chang , Tei-Wei Kuo
CPC分类号： G06F3/064 , G06F3/0619 , G06F3/0644 , G06F3/0659 , G06F3/0679 , G11C11/5628 , G11C16/10 , G11C16/3427 , G11C2211/5641 , G11C2211/5648
摘要： A data allocating method includes steps of: determining whether data to be written into a physical memory block is hot data or cold data; when the data is hot data, according to a hot data allocating order, searching at least one first empty sub-block from the physical memory block to allocate the data; when the data is cold data, according to a cold data allocating order, searching at least one second empty sub-block from the physical memory block to allocate the data.
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公开(公告)号：US20160154593A1
公开(公告)日：2016-06-02
申请号：US14811970
申请日：2015-07-29
发明人： Hung-Sheng Chang , Hsiang-Pang Li , Chun-Ta Lin , Yuan-Hao Chang , Tei-Wei Kuo
IPC分类号： G06F3/06
CPC分类号： G06F3/0673 , G06F3/0608 , G06F3/061 , G06F3/064 , G06F3/0641
摘要： A memory system is provided. The memory system includes a memory controller and a first memory block. The first memory block is configured to store a first data from a top of the first memory block in a top-down fashion. The first memory block is configured to store a first metadata corresponding to the first data from a bottom of the first memory block in a bottom-up fashion. The first data forms a first data area. The first metadata forms a first metadata area. And a first continuous space is formed between a bottom of the first data area and a top of the first metadata area.
摘要翻译： 提供了一种存储系统。 存储器系统包括存储器控制器和第一存储器块。 第一存储块被配置为以自顶向下的方式存储来自第一存储器块的顶部的第一数据。 第一存储器块被配置为以自下而上的方式存储来自第一存储器块的底部的与第一数据相对应的第一元数据。 第一数据形成第一数据区。 第一个元数据形成第一个元数据区域。 并且在第一数据区域的底部和第一元数据区域的顶部之间形成第一连续空间。
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公开(公告)号：US11550709B2
公开(公告)日：2023-01-10
申请号：US16655510
申请日：2019-10-17
发明人： Wei-Chen Wang , Hung-Sheng Chang , Chien-Chung Ho , Yuan-Hao Chang , Tei-Wei Kuo
摘要： A memory device includes: a memory array used for implementing neural networks (NN); and a controller coupled to the memory array. The controller is configured for: in updating and writing unrewritable data into the memory array in a training phase, marching the unrewritable data into a buffer zone of the memory array; and in updating and writing rewritable data into the memory array in the training phase, marching the rewritable data by skipping the buffer zone.
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