中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

126 records (took 0.022 seconds)

    Data processing unit with transparent root complex
    21.
    发明公开
    Data processing unit with transparent root complex 审中-公开

    公开(公告)号：US20240143526A1

    公开(公告)日：2024-05-02

    申请号：US17976909

    申请日：2022-10-31

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Liran Liss ,  Rabia Loulou ,  Idan Burstein ,  Tzuriel Katoa

    IPC: G06F13/28 ,  G06F13/42

    CPC classification number: G06F13/28 ,  G06F13/4221

    Abstract: Computing apparatus includes a central processing unit (CPU) and a root complex connected to the CPU and to a first peripheral component bus, which has at least a first downstream port for connection to at least one peripheral device. Switching logic has an upstream port for connection to a second downstream port on a second peripheral component bus of a host computer, and is connected to the root complex so that when a peripheral device is connected to the first downstream port on the first peripheral component bus, the switching logic presents the peripheral device to the host computer in an address space of the second peripheral component bus.

    Reliable Credit-Based Communication over Long-Haul Links
    22.
    发明公开
    Reliable Credit-Based Communication over Long-Haul Links 审中-公开

    公开(公告)号：US20230353499A1

    公开(公告)日：2023-11-02

    申请号：US17730246

    申请日：2022-04-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Liran Liss ,  Ortal Bashan ,  Aviad Levy ,  Lion Levi

    IPC: H04L47/10

    CPC classification number: H04L47/39

    Abstract: A communication apparatus includes input circuitry, an encapsulator, transmission circuitry and flow control circuitry. The input circuitry is to receive packets from a data source in accordance with a first communication protocol that employs credit-based flow control. The encapsulator is to buffer the packets in a memory buffer and to encapsulate the buffered packets in accordance with a second communication protocol. The transmission circuitry is to transmit the encapsulated packets over a communication link in accordance with the second communication protocol. The flow control circuitry is to receive from the encapsulator buffer status indications that are indicative of a fill level of the memory buffer, and to exchange credit messages with the data source, in accordance with the credit-based flow control of the first communication protocol, responsively to the buffer status indications.

    Efficient packet reordering using hints
    23.
    发明授权
    Efficient packet reordering using hints 有权

    公开(公告)号：US11792139B2

    公开(公告)日：2023-10-17

    申请号：US17582047

    申请日：2022-01-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Boris Pismenny ,  Ben Ben Ishay ,  Gal Yefet ,  Gil Kremer ,  Avi Urman ,  Yorai Itzhak Zack ,  Khalid Manaa ,  Liran Liss

    IPC: H04L69/22 ,  H04L49/90 ,  H04L49/9057

    CPC classification number: H04L49/9057 ,  H04L49/9042 ,  H04L69/22

    Abstract: A peripheral device coupled to a host includes a network interface, a packet processor, and a Data Processing Unit (DPU). The packet processor receives from a communication network, via the network interface, packets that originated from a source in an original order and received at the peripheral device in as order different from the original order. The packet processor splits the received packets into headers and payloads, sends the payloads for storage in a host memory and sends the headers without the payloads for storage in a DPU memory, and based on the headers produces a hint indicative of processing to be applied to the headers, by the DPU, for identifying the original order. Based on the hint, the DPU identifies the original order of the packets by applying the processing indicated by the hint to respective headers in the DPU memory, and notifies the host of the original order.

    METHODS AND SYSTEMS FOR INTER-STACK COMMUNICATION FOR LOGICAL VOLUME MANAGEMENT
    24.
    发明公开
    METHODS AND SYSTEMS FOR INTER-STACK COMMUNICATION FOR LOGICAL VOLUME MANAGEMENT 审中-公开

    公开(公告)号：US20230236769A1

    公开(公告)日：2023-07-27

    申请号：US17586417

    申请日：2022-01-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Omri Kahalon ,  Gal Shalom ,  Aviad Yehezkel ,  Liran Liss ,  Oren Duer ,  Rabie Loulou ,  Maxim Gurtovoy

    IPC: G06F3/06

    CPC classification number: G06F3/0689 ,  G06F3/067 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0613

    Abstract: Methods and systems provided herein involve extracting an input/output (I/O) operation from a packet received over an I/O pipeline, the I/O operation comprising either a read request to read data from at least one storage device or a write request to write data to the at least one storage device; determining that an address associated with the I/O operation exists in a lookup table that is provided for thin provisioning of the at least one storage device; performing one or more RAID calculations associated with the at least one storage device based on the address and the I/O operation; and accessing the at least one storage device to perform the I/O operation based on the one or more RAID calculations; and second processing component configured to carry out a second set of operations that occur when the address associated with the I/O operation does not exist in the lookup table.

    Method and apparatus for decrypting and authenticating a data record
    26.
    发明授权
    Method and apparatus for decrypting and authenticating a data record 有权

    公开(公告)号：US11658803B2

    公开(公告)日：2023-05-23

    申请号：US17198889

    申请日：2021-03-11

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Boris Pismenny ,  Liran Liss ,  Ilya Lesokhin

    IPC: H04L9/06 ,  H04L9/32

    CPC classification number: H04L9/0637 ,  H04L9/32 ,  H04L9/3242

    Abstract: A method, apparatus, and computer program product for processing a data record including encrypted and decrypted data is described. Various embodiments include receiving a data record including ciphertext and plaintext blocks and determining whether each block in the data record is a ciphertext block or a plaintext block. If a block is a ciphertext block, the ciphertext block is stored into a ciphertext record, decrypted into a plaintext block utilizing a decryption algorithm, and stored in a plaintext record. If the block is a plaintext block, the plaintext block is stored into the plaintext record, encrypted into a ciphertext block utilizing an encryption algorithm, and stored in the ciphertext record. Embodiments described also include authenticating the data record by passing each block of the ciphertext record to an authentication scheme and outputting the plaintext record to a destination application.

    Communication with accelerator via RDMA-based network adapter
    29.
    发明申请
    Communication with accelerator via RDMA-based network adapter 审中-公开

    公开(公告)号：US20200314181A1

    公开(公告)日：2020-10-01

    申请号：US16827912

    申请日：2020-03-24

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Haggai Eran ,  Dotan David Levi ,  Maxim Fudim ,  Liran Liss

    IPC: H04L29/08

    Abstract: A network node includes a bus switching element, and a network adapter, an accelerator and a host, all coupled to communicate via the bus switching element. The network adapter is configured to communicate with remote nodes over a communication network. The host is configured to establish a RDMA link between the accelerator and the RDMA endpoint by creating a Queue Pair (QP) to be used by the accelerator for communication with the RDMA endpoint via the RDMA link. The accelerator is configured to exchange data, via the network adapter, between a memory of the accelerator and a memory of the RDMA endpoint.

Patent Agency Ranking