中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

71 records (took 0.015 seconds)

    Explicit notification of operative conditions along a network path
    21.
    发明申请
    Explicit notification of operative conditions along a network path 有权

    公开(公告)号：US20210344782A1

    公开(公告)日：2021-11-04

    申请号：US17198292

    申请日：2021-03-11

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Yuval Shpigelman ,  Idan Burstein ,  Aviv Kfir ,  Liron Mula ,  Niv Aibester ,  Gil Levy

    IPC: H04L29/06 ,  H04L12/801 ,  H04L1/00

    Abstract: A network element includes circuitry and multiple ports. The multiple ports are configured to connect to a communication network. The circuitry is configured to receive via one of the ports a packet that originated from a source node and is destined to a destination node, the packet including a mark that is indicative of a cumulative state derived from at least bandwidth utilization conditions of output ports that were traversed by the packet along a path, from the source node up to the network element, to select a port for forwarding the packet toward the destination node, to update the mark of the packet based at least on a value of the mark in the received packet and on a local bandwidth utilization condition of the selected port, and to transmit the packet having the updated mark to the destination node via the selected port.

    Network Adapter with Time-Aware Packet-Processing Pipeline
    23.
    发明申请
    Network Adapter with Time-Aware Packet-Processing Pipeline 有权

    公开(公告)号：US20210243140A1

    公开(公告)日：2021-08-05

    申请号：US16782075

    申请日：2020-02-05

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula

    IPC: H04L12/861 ,  H04L29/06 ,  H04L12/741 ,  H04L12/46 ,  H04L12/931 ,  H04L12/801 ,  H04W56/00

    Abstract: A network adapter includes a host interface configured to communicate with a host, a network interface configured to communicate with a communication network, and packet processing circuitry. The packet processing circuitry is configured to receive a packet from the host via the host interface, or from the communication network via the network interface, to receive an indication of a network time used for synchronizing network elements in the communication network, to match the packet to a rule, the rule including a condition and an action, and to perform the action in response to the packet meeting the condition, wherein one or more of (i) the condition in the rule and (ii) the action in the rule, depend on the network time.

    Template-based packet parsing
    27.
    发明授权
    Template-based packet parsing 有权

    公开(公告)号：US12177322B2

    公开(公告)日：2024-12-24

    申请号：US18314834

    申请日：2023-05-10

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Gil Levy ,  Liron Mula ,  Barak Gafni

    IPC: G06F15/173 ,  H04L69/22 ,  H04L69/323 ,  H04L69/324

    Abstract: A parsing apparatus includes a packet-type identification circuit and a parser. The packet-type identification circuit is to receive a packet to be parsed, and to identify a packet type of the packet by extracting a packet-type identifier from a defined field in the packet. The parser is to store one or more parsing templates that specify parsing of one or more respective packet types. When the packet type of the packet corresponds to a parsing template among the stored parsing templates, the parser is to parse the packet in accordance with the stored parsing template. When the packet type of the packet does not correspond to any of the stored parsing templates, the parser is to parse the packet using an alternative parsing scheme.

    Analysis of Events in an Integrated Circuit Using Cause Tree and Buffer
    28.
    发明公开
    Analysis of Events in an Integrated Circuit Using Cause Tree and Buffer 审中-公开

    公开(公告)号：US20240152438A1

    公开(公告)日：2024-05-09

    申请号：US17981508

    申请日：2022-11-07

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Alon Singer ,  Ziv Battat ,  Liron Mula

    IPC: G06F11/30 ,  G06F11/07 ,  G06F11/34

    CPC classification number: G06F11/3037 ,  G06F11/079 ,  G06F11/3075 ,  G06F11/3409

    Abstract: An Integrated Circuit (IC) includes one or more functional hardware circuits, one or more processor cores, a cause-tree circuit, a memory buffer, and an analysis circuit. The processor cores are to handle events occurring in the functional hardware circuits. The cause-tree circuit includes leaf nodes, middle nodes and a root node. The leaf nodes are to collect the events from the one or more functional hardware circuits. The middle nodes are to coalesce the collected events and to deliver the events to the root node. The memory buffer is to buffer a plurality of the events delivered to the root node, so as to trigger the processor cores to handle the buffered events. The buffer analysis circuit is to analyze a performance of the cause-tree circuit based on the events buffered in the memory buffer.

    PACKET SWITCHES
    30.
    发明公开
    PACKET SWITCHES 审中-公开

    公开(公告)号：US20230224262A1

    公开(公告)日：2023-07-13

    申请号：US17648260

    申请日：2022-01-18

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Ioannis (Giannis) Patronas ,  Michael Gandelman ,  Liron Mula ,  Aviad Levy ,  Lion Levi ,  Jose Yallouz ,  Paraskevas Bakopoulos ,  Elad Mentovich

    IPC: H04L49/00 ,  H04L49/101

    CPC classification number: H04L49/3027 ,  H04L49/101 ,  H04L49/3018

    Abstract: Switches for performing packet switching and associated methods are provided. An example switch includes an ingress port for receiving a packet. The switch includes a plurality of egress ports for discharging the packet from the switch. The switch includes a plurality of egress queues with each egress queue associated with one of the plurality of egress ports. The switch includes a control plane configured to determine a descriptor associated with a packet, determine a first egress port from which to discharge the at least one packet and to transmit the descriptor to an egress queue associated with the first egress port. The switch includes a descriptor crossbar configured to transmit the descriptor from the egress queue to a second egress port of the plurality of egress ports. The switch includes a packet crossbar configured to transmit the at least one packet from the ingress port to the second egress port.

Patent Agency Ranking