公开(公告)号：US20170017584A1

公开(公告)日：2017-01-19

申请号：US15209467

申请日：2016-07-13

Applicant: Microchip Technology Incorporated

Inventor： Kevin Kilzer ,  Shyamsunder Ramanathan ,  Sai Karthik Rajaraman ,  Justin Milks

IPC: G06F13/10 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F13/102 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/4068 ,  G06F13/4282 ,  G06F13/4291

Abstract: A synchronous serial peripheral device has a transmission unit coupled with a data output line and a clock unit coupled with a clock line. The serial peripheral device transmits a minimum of a single transmission, wherein in a first operating mode the transmission unit and the clock unit are configurable to perform a data transmission with a data length that can be defined to be between one (1) and eight (8) bit.

Abstract translation: 同步串行外围设备具有与数据输出线耦合的传输单元和与时钟线耦合的时钟单元。 串行外围设备发送最少的单个传输，其中在第一操作模式中，传输单元和时钟单元可配置为执行具有数据长度的数据传输，数据长度可以被定义在1（1）到8（ 8）位。

公开(公告)号：US20160259741A1

公开(公告)日：2016-09-08

申请号：US15060553

申请日：2016-03-03

Applicant: Microchip Technology Incorporated

Inventor： Keith Curtis ,  Ashish Senapati ,  Anthony Garcia ,  Vijay Sarvepalli ,  Prashanth Pulipaka ,  Kevin Kilzer ,  David Forst ,  Rob Kennedy ,  Primo Castro ,  Aaron Barton

IPC: G06F13/26 ,  G06F9/30 ,  G06F9/22

CPC classification number: G06F13/26 ,  G06F9/22 ,  G06F9/30036 ,  G06F9/3013 ,  G06F13/24

Abstract: A microcontroller has a CPU with at least one interrupt input coupled with an interrupt controller, a plurality of peripherals, and a mode register comprising at least one bit controlling an operating mode of the microcontroller. The microcontroller is configured to operate in a first operating mode wherein upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the peripheral sets an associated interrupt flag, wherein the interrupt causes the CPU to branch to a predefined interrupt address associated with the interrupt input. In a second operating mode, upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the CPU receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.

Abstract translation: 微控制器具有CPU，其具有与中断控制器，多个外设耦合的至少一个中断输入，以及包括控制微控制器的操作模式的至少一个位的模式寄存器。 微控制器被配置为在第一操作模式下操作，其中当由微控制器的外设断言中断时，中断控制器将中断信号转发到CPU，并且外设设置相关联的中断标志，其中中断使CPU 分支到与中断输入相关联的预定义中断地址。 在第二操作模式中，当由微控制器的外设断言中断时，中断控制器将中断信号转发到CPU，并且CPU从产生中断的外设接收附加的中断信息，其中使用附加的中断信息 以生成向量地址。

公开(公告)号：US20160112060A1

公开(公告)日：2016-04-21

申请号：US14883842

申请日：2015-10-15

Applicant: Microchip Technology Incorporated

Inventor： James E. Bartling ,  Igor Wojewoda ,  Kevin Kilzer

IPC: H03M1/12 ,  G06F1/32

CPC classification number: H03M1/12 ,  G06F1/32 ,  H03K17/9622 ,  H03K2217/960725 ,  H03M1/00 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/50

Abstract: A micro-coded sequencer controls complex conversion sequences independent of a central processing unit (CPU). Micro-coding provides for easily adding new process steps and/or updating existing process steps. Such a programmable sequencer in combination with an analog-to-digital conversion module such as an analog-to-digital converter (ADC) or a charge time measurement unit (CTMU), and digital processing circuits may be configured to work independently of the CPU in combination with the micro-coded sequencer. Thereby providing self-sufficient operation in low power modes when the CPU and other high power modules are in a low power sleep mode. Such a peripheral can execute data collection and processing thereof, then wake the CPU only when needed, thereby saving power. Furthermore, this peripheral does not require CPU processing so that time critical applications that do require control by the CPU can operate more efficiently and with less operating overhead burden.

Abstract translation: 微编码序列器控制独立于中央处理单元（CPU）的复杂转换序列。 微编码提供了轻松添加新的流程步骤和/或更新现有的流程步骤。 与诸如模数转换器（ADC）或充电时间测量单元（CTMU）之类的模数转换模块和数字处理电路组合的这种可编程序排序器可被配置为独立于CPU 与微编码序列器结合使用。 因此，当CPU和其他高功率模块处于低功耗睡眠模式时，能够以低功耗模式提供自给自足的操作。 这样的外设可以执行数据收集和处理，然后在需要时唤醒CPU，从而节省电力。 此外，该外设不需要CPU处理，因此要求CPU进行控制的时间关键应用程序可以更有效地运行，同时减少运营负担。

公开(公告)号：US20140270048A1

公开(公告)日：2014-09-18

申请号：US14200317

申请日：2014-03-07

Applicant: Microchip Technology Incorporated

Inventor： Joseph Julicher ,  Kevin Kilzer ,  Cobus Van Eeden

IPC: H03K23/00

CPC classification number: H03K23/00 ,  G01P3/481 ,  G01P3/486 ,  G01P3/487 ,  G01P3/488 ,  G01P3/489 ,  H02P6/17 ,  H03K21/38 ,  H03K23/40

Abstract: A digital period divider has a first counter with R least significant bits (LSB) and P most significant bits (MSB) having a count input and a reset input, wherein the count input receives a first clock signal and the reset input receives a second clock signal; a latch having P bits and being coupled with the P bits of the first counter; a second counter having P bits and a count input and a reset input, wherein the count input receives the first clock signal; and a first comparator operable to compare the P bits of the latch with the P bits of the second counter and generating an output signal, wherein the output signal is also fed to the reset input of the second counter.

Abstract translation: 数字周期分配器具有具有R个最低有效位（LSB）和P个最高有效位（MSB）的第一计数器，其具有计数输入和复位输入，其中所述计数输入接收第一时钟信号，并且所述复位输入接收第二时钟 信号; 具有P位并与第一计数器的P位耦合的锁存器; 具有P位和计数输入和复位输入的第二计数器，其中所述计数输入接收所述第一时钟信号; 以及第一比较器，用于将锁存器的P位与第二计数器的P位进行比较并产生输出信号，其中输出信号也被馈送到第二计数器的复位输入。