公开(公告)号：US20210064455A1

公开(公告)日：2021-03-04

申请号：US16553731

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G06F11/07 ,  G06F11/10 ,  G11C11/409 ,  G11C5/06 ,  G11C15/04

Abstract: Methods, systems, and devices for error correction for content-addressable memory (CAM) are described. A CAM may store bit vectors as a set of subvectors, which each subvector stored in an independent aspect of the CAM, such as in a separate column or array of memory cells within the CAM. The CAM may similarly segment a queried input bit vector and identify, for each resulting input subvector, whether a matching subvector is stored by the CAM. The CAM may identify a match for the input bit vector when the number of matching subvectors satisfies a threshold. The CAM may validate a match based on comparing a stored bit vector corresponding to the identified match to the input bit vector. The stored bit vector may undergo error correction and may be stored in the CAM or another memory array, such as a dynamic random access memory (DRAM) array.

公开(公告)号：US20210056405A1

公开(公告)日：2021-02-25

申请号：US16545837

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Sean Stephen Eilert ,  Ameen D. Akel ,  Kenneth Marion Curewitz

IPC: G06N3/08 ,  G06F21/60

Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, inputs for the ANN can be obfuscated for centralized training of a master version of the ANN at a first computing device. A second computing device in the system includes memory that stores a local version of the ANN and user data for inputting into the local version. The second computing device includes a processor that extracts features from the user data and obfuscates the extracted features to generate obfuscated user data. The second device includes a transceiver that transmits the obfuscated user data. The first computing device includes a memory that stores the master version of the ANN, a transceiver that receives obfuscated user data transmitted from the second computing device, and a processor that trains the master version based on the received obfuscated user data using machine learning.

公开(公告)号：US20210056387A1

公开(公告)日：2021-02-25

申请号：US16545813

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Sean Stephen Eilert ,  Shivasankar Gunasekaran ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Hongyu Wang

IPC: G06N3/04 ,  G06N20/20

Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, changes to local versions of the ANN can be combined with a master version of the ANN. In the system, a first device can include memory that can store the master version, a second device can include memory that can store a local version of the ANN, and there can be many devices that store local versions of the ANN. The second device (or any other device of the system hosting a local version) can include a processor that can train the local version, and a transceiver that can transmit changes to the local version generated from the training. The first device can include a transceiver that can receive the changes to a local version, and a processing device that can combine the received changes with the master version.

公开(公告)号：US20200379919A1

公开(公告)日：2020-12-03

申请号：US16424420

申请日：2019-05-28

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Ameen D. Akel ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert ,  Dmitri Yudanov

IPC: G06F12/1027 ,  H04L29/08

Abstract: Systems, methods and apparatuses to accelerate accessing of borrowed memory over network connection are described. For example, a memory management unit (MMU) of a computing device can be configured to be connected both to the random access memory over a memory bus and to a computer network via a communication device. The computing device can borrow an amount of memory from a remote device over a network connection using the communication device; and applications running in the computing device can use virtual memory addresses mapped to the borrowed memory. When a virtual address mapped to the borrowed memory is used, the MMU translates the virtual address into a physical address and instruct the communication device to access the borrowed memory.

公开(公告)号：US20200342933A1

公开(公告)日：2020-10-29

申请号：US16926582

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel

IPC: G11C11/406 ,  G11C11/22 ,  G11C11/16 ,  G11C11/408 ,  G11C13/00

Abstract: Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages configured to be refreshed according to a refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.

公开(公告)号：US10109339B1

公开(公告)日：2018-10-23

申请号：US15663641

申请日：2017-07-28

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel

IPC: G11C11/40 ,  G11C11/406 ,  G11C11/22

Abstract: Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages having an refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.

公开(公告)号：US20250147897A1

公开(公告)日：2025-05-08

申请号：US19017035

申请日：2025-01-10

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Ameen D. Akel ,  Samuel E. Bradshaw ,  Kenneth Marion Curewitz ,  Sean Stephen Eilert

IPC: G06F12/1009 ,  G06F12/1027 ,  G06N5/043 ,  G06N5/045 ,  H04L67/1097 ,  H04L67/568 ,  H04W8/26

Abstract: Systems, methods and apparatuses of fine grain data migration in using memory as a service (MaaS) are described. For example, a memory status map can be used to identify the cache availability of sub-regions (e.g., cache lines) of a borrowed memory region (e.g., a borrowed remote memory page). Before accessing a virtual memory address in a sub-region, the memory status map is checked. If the sub-region has cache availability in the local memory, the memory management unit uses a physical memory address converted from the virtual memory address to make memory access. Otherwise, the sub-region is cached from the borrowed memory region to the local memory, before the physical memory address is used.

公开(公告)号：US12282682B2

公开(公告)日：2025-04-22

申请号：US18415285

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth M. Curewitz ,  Helena Caminal ,  Ameen D. Akel

IPC: G06F3/06

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.

公开(公告)号：US12217824B2

公开(公告)日：2025-02-04

申请号：US18160292

申请日：2023-01-26

Applicant: Micron Technology, Inc.

Inventor： Edmund Gieske ,  Amitava Majumdar ,  Cagdas Dirik ,  Sujeet Ayyapureddi ,  Yang Lu ,  Ameen D. Akel ,  Danilo Caraccio ,  Niccolo′ Izzo ,  Elliott C. Cooper-Balis ,  Markus H. Geiger

IPC: G11C29/52 ,  G11C7/22 ,  G11C7/24

Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.

公开(公告)号：US12182413B2

公开(公告)日：2024-12-31

申请号：US17897813

申请日：2022-08-29

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Yang Lu ,  Edmund Gieske ,  Cagdas Dirik ,  Ameen D. Akel ,  Elliott C. Cooper-Balis ,  Amitava Majumdar ,  Danilo Caraccio ,  Robert M. Walker

IPC: G06F11/07 ,  G06F3/06

Abstract: Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).