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公开(公告)号：US10854304B1
公开(公告)日：2020-12-01
申请号：US16701238
申请日：2019-12-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jun Xu , Yingda Dong
Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include performing a sense operation on a particular memory cell of a first string of series-connected memory cells selectively connected to a first data line, applying a first voltage level to the access line for a second memory cell of the first string, applying a second voltage level higher than the first voltage level to the access line for the particular memory cell, applying a third voltage level to the first data line concurrently with applying the first voltage level and concurrently with applying the second voltage level, and applying a fourth voltage level higher than the third voltage level to a second data line selectively connected to a second string of series-connected memory cells concurrently with applying the third voltage level to the first data line.
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公开(公告)号：US10685717B2
公开(公告)日：2020-06-16
申请号：US16411622
申请日：2019-05-14
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jun Xu
Abstract: Apparatus and methods of operating such apparatus include applying a first voltage level to a source connected to a first end of a string of series-connected memory cells, applying a second voltage level to a data line connected to a second end of the string of series-connected memory cells, and applying a third voltage level to a first access line coupled to a first memory cell of the string of series-connected memory cells concurrently with applying the first and second voltage levels, wherein the magnitude of the third voltage level is greater than the magnitude of both the first voltage level and the second voltage level, and wherein a polarity and the magnitude of the third voltage level are expected to decrease a threshold voltage of the first memory cell when concurrently applying the first, second and third voltage levels.
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23.发明授权公开(公告)号：US10418106B2
公开(公告)日：2019-09-17
申请号：US15569854
申请日：2017-08-28
Applicant: MICRON TECHNOLOGY, INC.
Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.
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公开(公告)号：US20180342303A1
公开(公告)日：2018-11-29
申请号：US16054206
申请日：2018-08-03
Applicant: Micron Technology, Inc.
Inventor： Jun Xu
Abstract: Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a plurality of units of information corresponding to a plurality of pages of information. The sensing signal can change from a first sensing magnitude to a second sensing magnitude and from the second sensing magnitude to a third sensing magnitude. The second sensing magnitude can be nonconsecutive from the first sensing magnitude and/or the third sensing magnitude can be nonconsecutive from the second sensing magnitude with respect to a plurality of sensing magnitudes corresponding to a plurality of charge storage states of the MLC.
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公开(公告)号：US09865355B2
公开(公告)日：2018-01-09
申请号：US14430448
申请日：2015-02-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yafeng Zhang , Liang Qiao , Chunyuan Hou , Jun Xu
CPC classification number: G11C16/225 , G11C16/14 , G11C16/30
Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.
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Patent Agency Ranking
公开(公告)号：US20160064094A1
公开(公告)日：2016-03-03
申请号：US14935744
申请日：2015-11-09
Applicant: Micron Technology, Inc.
Inventor： Jun Xu
CPC classification number: G11C16/26 , G11C11/56 , G11C11/5642
Abstract: Apparatuses and methods for nonconsecutive sensing of multilevel memory cells include methods of sensing a unit of information from a multilevel memory cell (MLC) using a sensing signal. The unit of information can correspond to a page of information. The MLC can store a plurality of units of information corresponding to a plurality of pages of information. The sensing signal can change from a first sensing magnitude to a second sensing magnitude and from the second sensing magnitude to a third sensing magnitude. The second sensing magnitude can be nonconsecutive from the first sensing magnitude and/or the third sensing magnitude can be nonconsecutive from the second sensing magnitude with respect to a plurality of sensing magnitudes corresponding to a plurality of charge storage states of the MLC.
Abstract translation: 用于多级存储器单元的非连续感测的装置和方法包括使用感测信号从多级存储器单元（MLC）感测信息单元的方法。 信息单元可以对应于一页信息。 MLC可以存储对应于多页信息的多个信息单元。 感测信号可以从第一感测幅度变化到第二感测幅度，并且从第二感测幅度变为第三感测量级。 第二检测幅度可以是与第一感测幅度非连续的，和/或第三感测幅度可以相对于对应于MLC的多个电荷存储状态的多个感测量级从第二感测幅度不连续。
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公开(公告)号：US11756612B2
公开(公告)日：2023-09-12
申请号：US17301139
申请日：2021-03-26
Applicant: Micron Technology, Inc.
Inventor： Jun Xu
CPC classification number: G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/3459
Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes one or more programming pulses to be applied to the set of the plurality of memory cells configured as MLC memory to program memory cells in the set of memory cells configured as MLC memory to respective programming levels of a plurality of programming levels as part of the program operation. Responsive to the one or more programming pulses being applied, the control logic further performs a program verify operation to verify whether the memory cell in the set of memory cells configured as MLC memory were programmed to the respective programming levels of the plurality of programming levels.
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公开(公告)号：US11205488B2
公开(公告)日：2021-12-21
申请号：US17066387
申请日：2020-10-08
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yafeng Zhang , Liang Qiao , Chunyuan Hou , Jun Xu
Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.
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公开(公告)号：US20200303014A1
公开(公告)日：2020-09-24
申请号：US16897772
申请日：2020-06-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jun Xu
Abstract: Apparatus including an array of memory cells comprising a plurality of strings of series-connected memory cells, a plurality of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of series-connected memory cells, and a controller configured during an erase operation of the plurality of strings of series-connected memory cells to apply a first voltage level to a node connected to an end of a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells, and apply a second voltage level to a particular access line of the plurality of access lines concurrently with applying the first voltage level to the node, wherein the second voltage level has a magnitude greater than the first voltage level, and is lower than the first voltage level.
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30.发明申请公开(公告)号：US20190287620A1
公开(公告)日：2019-09-19
申请号：US16433212
申请日：2019-06-06
Applicant: MICRON TECHNOLOGY, INC.
Abstract: Methods include programming a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and programming the second portion of memory cells in an order from the particular end to the different end. Methods further include incrementing a first read count and a second read count in response to performing a read operation on a memory cell of a block of memory cells, resetting the first read count in response to performing an erase operation on a first portion of memory cells of the block of memory cells, and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.
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