公开(公告)号：US20230050305A1

公开(公告)日：2023-02-16

申请号：US17402279

申请日：2021-08-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34

Abstract: A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.

公开(公告)号：US20230043877A1

公开(公告)日：2023-02-09

申请号：US17396386

申请日：2021-08-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang Xu ,  Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

IPC: G06F3/06 ,  G11C16/26 ,  G11C16/32 ,  G01K13/00

Abstract: A current operating characteristic value of a unit of the memory device is identified. An operating characteristic threshold value is identified from a set of operating characteristic thresholds, where the current operating characteristic value satisfies an operating characteristic threshold criterion that is based on the operating characteristic threshold value. A set of write-to-read (W2R) delay time thresholds that corresponds to the operating characteristic threshold value is identified from a plurality of sets of W2R delay time thresholds. Each of the W2R delay time thresholds in the set is associated with a corresponding read voltage level. A W2R delay time threshold associated with a W2R delay time threshold criterion is identified from the set of W2R delay time thresholds, where the W2R threshold criterion is satisfied by a current W2R delay time of the memory sub-system. A read voltage level associated with the identified W2R delay time threshold is identified.

公开(公告)号：US20230043238A1

公开(公告)日：2023-02-09

申请号：US17393013

申请日：2021-08-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Mikai Chen ,  Zhenming Zhou ,  Murong Lang ,  Zhenlei Shen

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4078

Abstract: A processing device of a memory sub-system is configured to determine, for a memory unit of the memory device, a plurality of write disturb counts associated with the memory unit, wherein each of the plurality of write disturb (WD) count is associated with a corresponding write disturb direction; compute, for the memory unit, a weighted WD count reflecting the plurality of write disturb counts; determine whether the weighted WD count meets a criterion; and responsive to determining that the weighted WD count meets the criterion, perform a refresh operation on the memory unit.

公开(公告)号：US11495316B1

公开(公告)日：2022-11-08

申请号：US17465020

申请日：2021-09-02

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Murong Lang ,  Zhenming Zhou

IPC: G11C29/10

Abstract: A system and method for optimizing seasoning trim values based on form factors in memory sub-system manufacturing. An example method includes selecting a baseline set of trim values based on a set of memory sub-system form factors; generating a first modified set of trim values by modifying a first trim value of the baseline trim values; instructing each memory sub-system to perform seasoning operations using the first modified set of trim values; responsive to determining that each memory sub-system passed failure scanning operations, generating a second modified set of trim values; instructing each memory sub-system to perform seasoning operations using the second modified set; responsive to determining that a memory sub-system failed the failure scanning operations, determining whether the failed memory sub-system is defective; and responsive to determining that the failed memory sub-system does is not defective, storing the first modified trim values for the set of form factors.

公开(公告)号：US11107543B2

公开(公告)日：2021-08-31

申请号：US17035501

申请日：2020-09-28

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Murong Lang

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/26 ,  G11C16/14 ,  G11C16/30 ,  G11C16/10 ,  G11C13/00 ,  G11C29/50

Abstract: A current demarcation voltage is determined, where the current demarcation voltage is to be applied to a memory cell for reading a state of the memory cell. Based on the current demarcation voltage and a space between a first threshold voltage distribution corresponding to a first state of the memory cell and a second threshold voltage distribution corresponding to a second state of the memory cell, a test demarcation voltage having a low error rate of reading the state of the memory cell is selected. The current demarcation voltage is set to correspond to the selected test demarcation voltage.

公开(公告)号：US20210225442A1

公开(公告)日：2021-07-22

申请号：US17222949

申请日：2021-04-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Murong Lang ,  Tingjun Xie ,  Zhenming Zhou

IPC: G11C13/00 ,  G11C7/10 ,  H01L27/24

Abstract: A method is disclosed that includes causing a first set of a plurality of voltage pulses to be applied to memory cells of a memory device, a voltage pulse of the first set of the voltage pulses placing the memory cells of the memory device at a voltage level associated with a defined voltage state. The method also includes determining a set of bit error rates associated with the memory cells of the memory device in view of a data mapping pattern for the memory cells of the memory device, wherein the data mapping pattern assigns a voltage level associated with a reset state to at least a portion of the memory cells of the memory device. The method further includes determining whether to apply one or more second sets of the voltage pulses to the memory cells of the memory device in view of a comparison between the set of bit error rates for the memory cells and a previously measured set of bit error rates for the memory cells.

公开(公告)号：US10908845B1

公开(公告)日：2021-02-02

申请号：US16552181

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou

IPC: G06F12/00 ,  G06F3/06 ,  G11C7/22

Abstract: A data structure is stored that includes a slope value corresponding to each die temperature of a set of die temperatures, where the slop value represents a change of a read voltage level as a function of a write-to-read delay time of a memory sub-system. In response to a read command, a current write-to-read delay time and a current die temperature are determined. Using the data structure, a stored slope value corresponding to the current die temperature is identified. An adjusted read voltage level is determined based at least in part on the stored slope value and the current write-to-read delay time. The read command is executed using the adjusted read voltage level.

公开(公告)号：US20250140320A1

公开(公告)日：2025-05-01

申请号：US18784434

申请日：2024-07-25

Applicant: Micron Technology, Inc.

Inventor： Hanping Chen ,  Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: Apparatuses and methods for performing sensing operations on partially programmed erase blocks are provided. One example apparatus can include a memory array comprising a plurality of erase blocks and a controller coupled to the memory array. The controller can be configured to apply a first sensing voltage to a first access line of a first group of access lines corresponding to the first erase block during a first sensing operation on the first erase block that is partially programmed, apply a first pass voltage to a number of programmed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation, and apply a second pass voltage a number of unprogrammed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation.

公开(公告)号：US12217794B2

公开(公告)日：2025-02-04

申请号：US18425619

申请日：2024-01-29

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Zhenming Zhou ,  Jian Huang ,  Tingjun Xie ,  Jiangli Zhu ,  Nagendra Prasad Ganesh Rao ,  Sead Zildzic

IPC: G11C11/56

Abstract: A difference between a recorded time stamp for a first set of memory cells comprised by an open translation unit (TU) of memory cells and a current time stamp for the open TU is determined, wherein the first set of memory cells comprises a most recently programmed set of memory cells. It is determined, based on a current temperature for the open TU and the difference between the recorded time stamp and the current time stamp, that a second set of memory cells comprised by the open TU is in a coarse programming state. A programming operation is performed on the second set of memory cells using a reduced programming state verify level and a reduced programming state gate step size associated with the second set of memory cells.

公开(公告)号：US12198777B2

公开(公告)日：2025-01-14

申请号：US17812612

申请日：2022-07-14

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Murong Lang ,  Zhenming Zhou ,  Ting Luo

IPC: G11C16/10 ,  G11C16/26 ,  G11C29/00 ,  G11C29/50 ,  G11C29/52

Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.