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    Apparatuses including output drivers and methods for providing output data signals
    23.
    发明授权
    Apparatuses including output drivers and methods for providing output data signals 有权

    公开(公告)号：US12237001B2

    公开(公告)日：2025-02-25

    申请号：US17700289

    申请日：2022-03-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Shun Nishimura ,  Yoshinori Matsui

    IPC: G11C11/4096 ,  G11C11/4093 ,  H03K19/003

    Abstract: Apparatuses including output drivers and methods for providing output data signals are described. An example apparatus includes a high logic level driver, a low logic level driver, and an intermediate logic level driver. The high logic level driver is provided a first voltage and provides a high logic level voltage to a data terminal when activated. The low logic level driver is provided a second voltage and provides a low logic level voltage to the data terminal when activated. The intermediate logic level driver is provided a third voltage having a magnitude that is between the first and second voltages, and provides an intermediate logic level voltage to the data terminal when activated. Each of the high, low, and intermediate logic level drivers are configured to be respectively activated based on one or more of a plurality of control signals.

    Semiconductor memory device including output buffer
    24.
    发明授权
    Semiconductor memory device including output buffer 有权

    公开(公告)号：US11087802B2

    公开(公告)日：2021-08-10

    申请号：US16363961

    申请日：2019-03-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tetsuya Arai ,  Junki Taniguchi

    IPC: G11C7/10 ,  G06F1/26 ,  G01R31/319

    Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

    Semiconductor device including buffer circuit
    25.
    发明授权
    Semiconductor device including buffer circuit 有权

    公开(公告)号：US11057038B2

    公开(公告)日：2021-07-06

    申请号：US16656415

    申请日：2019-10-17

    Applicant: Micron Technology, Inc.

    Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Junki Taniguchi

    IPC: H03K19/00 ,  G11C5/14 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50

    Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.

    Apparatuses and methods for pre-emphasis control
    26.
    发明授权
    Apparatuses and methods for pre-emphasis control 有权

    公开(公告)号：US11031054B1

    公开(公告)日：2021-06-08

    申请号：US16749811

    申请日：2020-01-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tetsuya Arai ,  Junki Taniguchi

    IPC: G11C7/00 ,  G11C7/12 ,  G11C11/4074 ,  G11C7/10 ,  G11C7/22

    Abstract: Apparatuses and methods for pre-emphasis control are described. An example apparatus includes a pull-up circuit and a pull-down circuit. The pull-up circuit is configured to receive a pull-up data activation signal and drive a data terminal to a pull-up voltage responsive to an active pull-up data activation signal. The pull-down circuit is configured to receive a pull-down activation signal and drive a data terminal to a pull-down voltage responsive to an active pull-down data activation signal. The example apparatus further includes a pull-up pre-emphasis circuit that includes a pre-emphasis timing control circuit configured to provide a timing control signal, and further includes a pull-up logic circuit. A pull-up pre-emphasis control signal based on pull-up data activation signal is provided to control providing pull-up pre-emphasis for greater than one unit interval of data when the pull-up data activation signal remains active for greater than one unit interval.

    SEMICONDUCTOR DEVICE INCLUDING BUFFER CIRCUIT
    28.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING BUFFER CIRCUIT 审中-公开

    公开(公告)号：US20200052698A1

    公开(公告)日：2020-02-13

    申请号：US16656415

    申请日：2019-10-17

    Applicant: Micron Technology, Inc.

    Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Junki Taniguchi

    IPC: H03K19/00 ,  G11C5/14 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50

    Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.

    Semiconductor device including buffer circuit
    29.
    发明授权
    Semiconductor device including buffer circuit 有权

    公开(公告)号：US10511306B2

    公开(公告)日：2019-12-17

    申请号：US15220310

    申请日：2016-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Tetsuya Arai ,  Shuichi Tsukada ,  Junki Taniguchi

    IPC: H03K19/00 ,  G11C5/14 ,  G11C7/10 ,  G11C29/02 ,  G11C29/50

    Abstract: A device includes a power supply line, an output terminal, a circuit configured to perform a logic operation on a first signal and a second signal to produce a third signal, first, second and third transistors. The first transistor is coupled between the power supply line and the output terminal and includes a control gate supplied with the third signal. The second and third transistors are coupled in series between the power supply line and the output terminal. The second transistor includes a control gate supplied with the first signal and the third transistor includes a control gate supplied with a fourth signal that is different from each of the first, second and third signals.

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