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    Output buffer circuit with non-target ODT function
    1.
    发明授权
    Output buffer circuit with non-target ODT function 有权

    公开(公告)号：US10777257B1

    公开(公告)日：2020-09-15

    申请号：US16707783

    申请日：2019-12-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tetsuya Arai ,  Junki Taniguchi

    IPC: G11C11/40 ,  H03K19/177 ,  G11C11/4093 ,  G11C11/4096 ,  H03K19/00 ,  H03K3/037 ,  H03K19/094 ,  H03K19/17772 ,  H03H11/28 ,  H03K19/17784

    Abstract: Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.

    Semiconductor memory device including output buffer
    2.
    发明授权
    Semiconductor memory device including output buffer 有权

    公开(公告)号：US10269395B2

    公开(公告)日：2019-04-23

    申请号：US14705762

    申请日：2015-05-06

    Applicant: Micron Technology, Inc.

    Inventor： Tetsuya Arai ,  Junki Taniguchi

    IPC: G01R31/319 ,  G11C7/10 ,  G06F1/26

    Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

    DEVICE HAVING MULTIPLE CHANNELS WITH CALIBRATION CIRCUIT SHARED BY MULTIPLE CHANNELS
    3.
    发明申请
    DEVICE HAVING MULTIPLE CHANNELS WITH CALIBRATION CIRCUIT SHARED BY MULTIPLE CHANNELS 有权
    具有多个通道共享的校准电路的多通道器件

    公开(公告)号：US20150340069A1

    公开(公告)日：2015-11-26

    申请号：US14695837

    申请日：2015-04-24

    Applicant: Micron Technology, Inc.

    Inventor： TETSUYA ARAI ,  Junki Taniguchi

    IPC: G11C7/04

    CPC classification number: G11C7/04 ,  G11C5/025 ,  G11C11/401 ,  G11C11/4093 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/2254 ,  H03K19/018507 ,  H03K19/018585

    Abstract: An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.

    Abstract translation: 一种装置包括第一通道，第二通道和校准电路。 第一通道包括第一命令控制电路。 第二通道包括独立于第一命令控制电路的第二命令控制电路。 所述校准电路由所述第一通道和所述第二通道共用，以响应于响应于来自所述第一命令控制电路的第一校准命令产生的校准命令和来自所述第二命令控制电路的第二校准命令产生校准代码。

    High speed signal adjustment circuit
    4.
    发明授权
    High speed signal adjustment circuit 有权

    公开(公告)号：US11088681B2

    公开(公告)日：2021-08-10

    申请号：US16358568

    申请日：2019-03-19

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tetsuya Arai ,  Junki Taniguchi

    IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08 ,  H03K5/135 ,  H03K3/037 ,  G11C7/10 ,  H03K17/687 ,  H03M9/00

    Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

    SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE INCLUDING OUTPUT BUFFER 审中-公开
    半导体存储器件，包括输出缓冲器

    公开(公告)号：US20150323971A1

    公开(公告)日：2015-11-12

    申请号：US14705762

    申请日：2015-05-06

    Applicant: Micron Technology, Inc.

    Inventor： TETSUYA ARAI ,  Junki Taniguchi

    IPC: G06F1/26

    CPC classification number: G11C7/1057 ,  G01R31/3191 ,  G06F1/266 ,  G11C2207/2254

    Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

    Abstract translation: 一种装置包括外部端子，具有对应于代码信号的阻抗的输出电路，以及校准电路，其被配置为响应于外部端子处的电压与参考电压的比较而产生代码信号，所述比较由 在第一模式中的第一循环周期和在第二模式中比第一循环周期长的第二循环。

    High speed signal adjustment circuit
    8.
    发明授权
    High speed signal adjustment circuit 有权

    公开(公告)号：US11552626B2

    公开(公告)日：2023-01-10

    申请号：US17396516

    申请日：2021-08-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tetsuya Arai ,  Junki Taniguchi

    IPC: H03K5/135 ,  H03K3/037 ,  G11C7/10 ,  H03K17/687 ,  H03M9/00

    Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

    High Speed Signal Adjustment Circuit
    9.
    发明申请
    High Speed Signal Adjustment Circuit 有权

    公开(公告)号：US20210367587A1

    公开(公告)日：2021-11-25

    申请号：US17396516

    申请日：2021-08-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tetsuya Arai ,  Junki Taniguchi

    IPC: H03K5/135 ,  H03K3/037 ,  G11C7/10 ,  H03K17/687 ,  H03M9/00

    Abstract: Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

    Output buffer circuit with non-target ODT function
    10.
    发明授权
    Output buffer circuit with non-target ODT function 有权

    公开(公告)号：US10529412B1

    公开(公告)日：2020-01-07

    申请号：US16379635

    申请日：2019-04-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Tetsuya Arai ,  Junki Taniguchi

    IPC: G11C11/40 ,  H03K19/177 ,  G11C11/4093 ,  H03H11/28 ,  G11C11/4096 ,  H03K19/00 ,  H03K3/037 ,  H03K19/094

    Abstract: Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.

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