-
公开(公告)号：US20200020367A1
公开(公告)日：2020-01-16
申请号：US16530525
申请日：2019-08-02
Applicant: Micron Technology, Inc.
Inventor： Robert Nasry Hasbun , Timothy M. Hollis , Jeffrey P. Wright , Dean D. Gans
IPC: G11C7/10 , G11C11/22 , G06F1/3234 , G06F13/42
Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).
-
公开(公告)号：US20190287584A1
公开(公告)日：2019-09-19
申请号：US16058588
申请日：2018-08-08
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis
IPC: G11C7/10 , H01L25/065 , H01L23/48 , G11C7/22 , G06F13/16
Abstract: Methods, systems, and apparatuses for a memory device that is configurable based on the type of substrate used to couple the memory device with a host device are described. The reconfigurable memory device may include a plurality of components for different configurations. Various components of the reconfigurable memory die may be activated/deactivated based on a type of substrate used in the memory device. The memory device may include an input/output (I/O) interface that is variously configurable. A first configuration may cause the memory device to communicate signals modulated using a first modulation scheme across a channel of a first width. A second configuration may cause the memory device to communicate signals modulated using a second modulation scheme across a channel of a second width. The I/O interface may include one or more switching components to selectively couple pins of a channel together and/or selectively couple components to various pins.
-
公开(公告)号：US20190273642A1
公开(公告)日：2019-09-05
申请号：US16419870
申请日：2019-05-22
Applicant: Micron Technology, Inc.
Inventor： Robert Nasry Hasbun , Timothy M. Hollis , Jeffrey P. Wright , Dean D. Gans
IPC: H04L27/04 , G11C8/12 , G06F13/38 , G11C5/06 , G06F12/02 , H04L27/06 , H04L27/02 , H04L25/49 , G11C7/10 , G06F13/16
Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.
-
公开(公告)号：US10347304B2
公开(公告)日：2019-07-09
申请号：US16045468
申请日：2018-07-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Timothy M. Hollis
Abstract: Apparatuses and methods for a multi-level communication architectures are disclosed herein. An example apparatus may include an input/output (I/O) circuit comprising a driver circuit configured to convert a first bitstream directed to a first memory device and a second bitstream directed to a second memory device into a single multilevel signal. The driver circuit is further configured to drive the multilevel signal onto a signal line coupled to the first memory device and to the second memory device using a driver configured to drive more than two voltages.
-
公开(公告)号：US20190044769A1
公开(公告)日：2019-02-07
申请号：US15893089
申请日：2018-02-09
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis
Abstract: Methods, systems, and devices for improving uniformity between levels of a multi-level signal are described. Techniques are provided herein to unify peak-to-peak voltage differences between the amplitudes of data transmitted using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
-
Patent Agency Ranking
公开(公告)号：US20190044764A1
公开(公告)日：2019-02-07
申请号：US15854600
申请日：2017-12-26
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis , Markus Balb , Ralf Ebert
CPC classification number: H04L25/4917 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C7/1096 , H04L25/4921
Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.
-
公开(公告)号：US20170177301A1
公开(公告)日：2017-06-22
申请号：US15431421
申请日：2017-02-13
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis
CPC classification number: G06F5/06 , G06F13/38 , G06F13/385 , G06F13/4273 , H04L12/4013 , H04L25/0272 , H04L67/288 , H04Q2213/13036 , H04Q2213/13305
Abstract: Methods and apparatus to transfer data between a first device and a second device, is disclosed. An apparatus according to various embodiments may comprise a first device and a second device. The first device may comprise at least one first non-differential transmitter coupled to a first channel, at least one second non-differential transmitter coupled to a second channel, and at least one differential receiver to receive a data bit and its complement on the first and second channels in parallel. The second device may comprise at least one first non-differential receiver coupled to the first channel, at least one second non-differential receiver coupled to the second channel, and at least one differential transmitter to transmit a data bit and its complement on the first and second channels in parallel.
-
公开(公告)号：US09509535B2
公开(公告)日：2016-11-29
申请号：US14918346
申请日：2015-10-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Timothy M. Hollis
CPC classification number: H04L25/4917 , H03K19/0002 , H04L25/4923 , H04L25/4927
Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.
-
公开(公告)号：US09276568B2
公开(公告)日：2016-03-01
申请号：US14543004
申请日：2014-11-17
Applicant: Micron Technology, Inc.
Inventor： Timothy M. Hollis
CPC classification number: H03K5/2472 , G06F13/00 , G06F13/4072 , G11C5/14 , H04B1/16 , H04L25/06
Abstract: A reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vreffrom a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the Vref generator can be used in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (e.g., Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply.
Abstract translation: 公开了一种用于通信系统中的单端接收机的参考电压（Vref）发生器。 一个示例中的Vref发生器包括用于向电阻器Rb提供电流I以产生Vref电压（I * Rb）的级联电流源。 由于电流源将Vreffrom隔离为两个电源中的第一个，所以Vref将仅随耦合到Rb的第二个电源而变化。 因此，Vref发生器可以用于采用参考该第二电源但具有解耦第一电源的信号的系统。 例如，在其中第二电源（例如，Vssq）对于两个装置是公共的但是第一电源（Vddq）不是）的通信系统中，所公开的Vref发生器产生用于跟踪Vssq而不是第一电源 。
-
公开(公告)号：US09270506B2
公开(公告)日：2016-02-23
申请号：US14308122
申请日：2014-06-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Timothy M. Hollis
IPC: H04L25/49 , H04L1/22 , G11C5/02 , H01L21/66 , H01L25/065 , H04L25/02 , H04L27/02 , G06F11/20 , H01L23/48
CPC classification number: H04L25/4917 , G11C5/02 , H01L22/22 , H01L23/481 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H04L1/22 , H04L25/0264 , H01L2924/00
Abstract: Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors.
Abstract translation: 公开了诸如涉及3-D集成电路的装置。 一种这样的设备包括：第一模具，其包括穿过其形成的多个垂直连接件。 该装置还包括配置成将多个数据位编码为多位符号的第一电路，并将多位符号提供给两个或多个垂直连接器。 所述设备还包括被配置为从所述两个或更多个垂直连接器中的至少一个接收多位符号并将多位符号解码为多个数据位的第二电路。 该设备提供增强的可修复性，没有或多少冗余的垂直连接器，从而避免了对“有故障的”垂直连接器进行“即时”或现场维修的需要。
-
-
-
-
-
-
-
-
-
Search Results
183
records
(took 0.037 seconds)
