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    MODIFIABLE REPAIR SOLUTIONS FOR A MEMORY ARRAY
    21.
    发明申请
    MODIFIABLE REPAIR SOLUTIONS FOR A MEMORY ARRAY 有权

    公开(公告)号：US20210407615A1

    公开(公告)日：2021-12-30

    申请号：US16914927

    申请日：2020-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning ,  Troy D. Larsen ,  Jonathan D. Harms ,  Glen E. Hush ,  Timothy P. Finkbeiner

    IPC: G11C29/44 ,  G11C29/42 ,  G11C29/00 ,  G11C29/18

    Abstract: Methods, systems, and devices for modifiable repair solutions for a memory array are described to support storing repair information for a memory array within the memory array itself. A memory device may include the memory array and an on-die microprocessor, where the microprocessor may retrieve the repair information from the memory array and write the repair information to repair circuitry used for identifying defective memory addresses. The microprocessor may support techniques for identifying additional defects and updating the repair information during operation of the memory array. For example, the microprocessor may identify additional defects based on errors associated with one or more memory cells of the memory array or based on testing performed on one or more memory cells of the memory array. In some cases, a host device may identify additional defects and may notify the microprocessor of the additional defects.

    Coherent memory access
    24.
    发明授权
    Coherent memory access 有权

    公开(公告)号：US10769071B2

    公开(公告)日：2020-09-08

    申请号：US16156654

    申请日：2018-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Timothy P. Finkbeiner ,  Troy D. Larsen

    IPC: G06F12/00 ,  G06F12/0877

    Abstract: Apparatuses and methods related to providing coherent memory access. An apparatus for providing coherent memory access can include a memory array, a first processing resource, a first cache line and a second cache line coupled to the memory array, a first cache controller, and a second cache controller. The first cache controller coupled to the first processing resource and to the first cache line can be configured to provide coherent access to data stored in the second cache line and corresponding to a memory address. A second cache controller coupled through an interface to a second processing resource external to the apparatus and coupled to the second cache line can be configured to provide coherent access to the data stored in the first cache line and corresponding to the memory address. Coherent access can be provided using a first cache line address register of the first cache controller which stores the memory address and a second cache line address register of the second cache controller which also stores the memory address.

    Memory address translation
    27.
    发明授权
    Memory address translation 有权

    公开(公告)号：US09274973B2

    公开(公告)日：2016-03-01

    申请号：US14269445

    申请日：2014-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning ,  Martin L. Culley ,  Troy D. Larsen

    IPC: G06F12/00 ,  G06F12/10 ,  G06F12/02

    CPC classification number: G06F12/1045 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1004 ,  G06F2212/7201 ,  Y02D10/13

    Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

    Codewords that span pages of memory
    28.
    发明授权
    Codewords that span pages of memory 有权
    内存页面的代码字

    公开(公告)号：US09088303B2

    公开(公告)日：2015-07-21

    申请号：US13780726

    申请日：2013-02-28

    Applicant: Micron Technology, Inc.

    Inventor： Troy D. Larsen ,  Martin L. Culley

    IPC: G11C29/00 ,  H03M13/29 ,  H03M13/09 ,  H03M13/11 ,  H03M13/15

    CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906

    Abstract: The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a primary codeword to a first page in a first block of memory and writing a second portion of the primary codeword to a second page in a second block of memory. The primary codeword can be included in a secondary codeword. The method can include writing a first portion of the secondary codeword in the memory and writing a second portion of the secondary codeword to a different page and block of the memory than the first portion of the secondary codeword.

    Abstract translation: 本公开包括跨越存储器页面的码字的装置和方法。 许多方法包括将主码字的第一部分写入第一存储器块中的第一页，并将主码字的第二部分写入第二存储器块中的第二页。 主码字可以被包括在次码字中。 该方法可以包括将次码字的第一部分写入存储器中，并将次码字的第二部分写入与辅助码字的第一部分不同的存储器页和块。

    MEMORY ADDRESS TRANSLATION
    29.
    发明申请
    MEMORY ADDRESS TRANSLATION 有权
    存储地址翻译

    公开(公告)号：US20140297990A1

    公开(公告)日：2014-10-02

    申请号：US14269445

    申请日：2014-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Troy A. Manning ,  Martin L. Culley ,  Troy D. Larsen

    IPC: G06F12/10

    CPC classification number: G06F12/1045 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1004 ,  G06F2212/7201 ,  Y02D10/13

    Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

    Abstract translation: 本公开包括用于存储器地址转换的装置，系统和方法。 一个或多个实施例包括存储器阵列和耦合到阵列的控制器。 阵列包括具有多个记录的第一表，其中每个记录包括多个条目，其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。 控制器包括具有多个记录的第二表，其中每个记录包括多个条目，其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。 控制器还包括具有多个记录的第三表，其中每个记录包括多个条目，其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。

    CODEWORDS THAT SPAN PAGES OF MEMORY
    30.
    发明申请
    CODEWORDS THAT SPAN PAGES OF MEMORY 有权
    编写存储空间页码

    公开(公告)号：US20140245097A1

    公开(公告)日：2014-08-28

    申请号：US13780726

    申请日：2013-02-28

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Troy D. Larsen ,  Martin L. Culley

    IPC: H03M13/29

    CPC classification number: G06F11/1068 ,  G11C29/52 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/2906

    Abstract: The present disclosure includes apparatuses and methods for codewords that span pages of memory. A number of methods include writing a first portion of a primary codeword to a first page in a first block of memory and writing a second portion of the primary codeword to a second page in a second block of memory. The primary codeword can be included in a secondary codeword. The method can include writing a first portion of the secondary codeword in the memory and writing a second portion of the secondary codeword to a different page and block of the memory than the first portion of the secondary codeword.

    Abstract translation: 本公开包括跨越存储器页面的码字的装置和方法。 许多方法包括将主码字的第一部分写入第一存储器块中的第一页，并将主码字的第二部分写入第二存储器块中的第二页。 主码字可以被包括在次码字中。 该方法可以包括将次码字的第一部分写入存储器中，并将次码字的第二部分写入与辅助码字的第一部分不同的存储器页和块。

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